The challenges posed by high chip heat fluxes and ever more stringent performance and reliability constraints make thermal management a key enabling technology in the development of microelectronic systems for the twenty‐first century. Thus, thermal packaging efforts must be performed in the context of the salient trends and parameters that characterize the IC technology and the electronic products industry.
Recent road‐mapping efforts, have affirmed the expectation that improvements in CMOS semiconductor technology will continue unabated into the early part of the twenty‐first century. Exploiting the potential of this IC technology, with the attendant increase in chip size, switching speed, and transistor density, will necessitate significant improvements in packaging technology.
This article discusses findings of some immersion cooling studies carried out to define the potential of direct liquid cooling of three-dimensional chip stacks. Four possible immersion cooling strategies were assessed. These included two active cooling strategies and two passive cooling strategies. The cooling densities for all four immersion cooling techniques were determined assuming the use of Fluorinert FC-72, a commonly used perfluorinated dielectric liquid. For passive systems, the cooling densities ranged from 25 W/cm3 for natural convection to 200–400 W/cm3 for pool boiling. For active technologies, the densities were 100–300 W/cm3 for forced convection and more than 2000 W/cm3 for flow boiling. It was found that the optimum die spacings for both single- and two-phase direct cooling was in the range of 0.2–0.6 mm for typical microelectronics geometries, though substantial cooling densities could be achieved at less-than-optimum spacings.
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