In recent years, a considerable research effort has shown the energy benefits of implementing neural networks with memristors or other emerging memory technologies. However, for extreme-edge applications with high uncertainty, access to reduced amounts of data, and where explainable decisions are required, neural networks may not provide an acceptable form of intelligence. Bayesian reasoning can solve these concerns, but it is computationally expensive and, unlike neural networks, does not translate naturally to memristor-based architectures. In this work, we introduce, demonstrate experimentally on a fully fabricated hybrid CMOS-memristor system, and analyze a Bayesian machine designed for highly-energy efficient Bayesian reasoning. The architecture of the machine is obtained by writing Bayes' law in a way making its implementation natural by the principles of distributed memory and stochastic computing, allowing the circuit to function using solely local memory and minimal data movement. Measurements on a fabricated small-scale Bayesian machine featuring 2,048 memristors and 30,080 transistors show the viability of this approach and the possibility of overcoming the challenges associated with its design: the inherent imperfections of memristors, as well as the need to distribute very locally higher-than-nominal supply voltages. The design of a scaled-up version of the machine shows its outstanding energy efficiency on a real-life gesture recognition task: a gesture can be recognized using 5,000 times less energy than using a microcontroller unit. The Bayesian machine also features several desirable features, e.g., instant on/off operation, compatibility with low supply voltages, and resilience to single-event upsets. These results open the road for Bayesian reasoning as an attractive way for energy-efficient, robust, and explainable intelligence at the edge.
Figure 1: a Optical microscopy photograph, b layout view, and c schematic of the hybrid Memristor-CMOS die. d Electron microscopy image of a memristor in our hybrid memristor/CMOS process. e Measurement of memristor resistance as a function of number of RESET programming pulses, for implementing a synaptic learning rule. f Illustration of memristor programming states. g Schematic of the analog mode circuitry, with shift registers selecting inputs via Multiplexers . h Schematic of the digital mode circuitry, with a complementary 2T2R memristor basic cell. i Schematics of the sensing circuitry with XNOR logic-in-memory feature. j Schematic of the level shifters, used for shifting digital nominal voltage to forming and programming voltages of memristors. k Voltages applied for forming or programming a complementary cell in the digital mode. l Measurements setup of the prototyping platform. m Memristor endurance study, using the digital mode for programming and the analog mode for resistance measurements.
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