Logical Execution Time (LET) is a timed programming abstraction, which features predictable and composable timing. It has recently gained considerable attention in the automotive industry, where it was successfully applied to master the distribution of software applications on multi-core electronic control units. However, the LET abstraction in its conventional form is only valid within the scope of a single component. With the recent introduction of System-level Logical Execution Time (SL LET), the concept could be transferred to a system-wide scope. This article improves over a first paper on SL LET, by providing matured definitions and an extensive discussion of the concept. It also features a comprehensive evaluation exploring the impacts of SL LET with regard to design, verification, performance, and implementability. The evaluation goes far beyond the contexts in which LET was originally applied. Indeed, SL LET allows us to address many open challenges in the design and verification of complex embedded hardware/software systems addressing predictability, synchronization, composability, and extensibility. Furthermore, we investigate performance trade-offs, and we quantify implementation costs by providing an analysis of the additionally required buffers.
To cope with growing computing performance requirements, cyber-physical systems architectures are moving toward heterogeneous high-performance computer architectures and networks. Such architectures, however, incur intricate side effects that challenge traditional software design and integration. The programming paradigm can take a key role in mastering software design, as experience in automotive design demonstrates. To cope with the integration challenge, this industry has started introducing a programming paradigm that efficiently preserves application data flow under platform integration and changes with minimum performance loss. This article will revisit this paradigm that is currently used for lock-free multicore programming and explain its extension to the system level. It will then explore its application to two important developments in industrial design. This article will conclude with an evaluation of its properties, its overhead, and its application toward a robust design process. KEYWORDS | Automation; industry 4.0; real-time (RT) programming abstractions; smart manufacturing; system integration; system-level logical execution time (SL LET). NOMENCLATURE ADAS Advanced driver assistance system. API Application programming interface. This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. Gemlau et al.: Platform Programming Paradigm for Heterogeneous Systems Integration PDP Participant discovery protocol. pHRI Physical human-robot interaction. PIM Platform-independent model. PLC Programmable logic controller. PSM Platform-specific model. PTP Precision time protocol. QoS Quality-of-service. RAMI 4.0 Reference architecture model industry 4.0. RE Runnable entity. ROS 2 Robot operating system 2. RTE Runtime environment. RTPS Real-time publish subscribe protocol. RT Real time. SAE Society of Automotive Engineers. SDN Software defined networking. SL LET System-level logical execution time. (SL) LET (System-level) logical execution time. SOME/IP Scalable service-oriented middleware over IP. SPNP Static priority nonpreemptive. SPP Static priority preemptive. SW-C Software component. SysML Systems modeling language. TAI Temps Atomique International. TAS Time aware shaper. TDL Timing definition language. TDMA Time division multiple access. TSN Time-sensitive networking. TTA Time-triggered architecture. UDP User datagram protocol. UML Unified modeling language. VFB Virtual functional bus. WCET Worst case execution time. WCRT Worst case response time. XML Extensible markup language. ZET Zero execution time.
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