Instituting dimensional reductions in the layout of CMOS semiconductor chips can lead to unwanted conduction paths significant enough to impact the performance and reliability of the subsequent fabricated integrated circuit. Positive location and identification of the suspect areas is required for the determination of root cause and to enable corrective action to eliminate or minimize the unwanted conduction paths. Empirical methods have to be employed to identify suspect areas since EDA vendors do not have CAD tools sufficiently capable of identifying the suspect areas during the design phase of a complicated high performance integrated circuit.Applying varied thermal imaging procedures and analytical techniques on specially assembled bare chips with defined limited performance identified problematic chip substrate regions and subsequent current conduction through the substrate as the problem in those regions. Corrective chip design layout and assembly techniques were instituted to achieve the required isolation.Although corrective action was achieved through chip design layout modifications, an outline of the wafer processing technology employed will be presented to designate the questionable areas with possible fabrication alterations to avoid the conduction paths encountered.
A method to detect defects affecting laser diode radiation has been devised by imaging the induced luminescence resulting from a scanning electron beam. Electron Beam Induced Luminescence (EBIL) involves imaging the current from a sensor diode as the SEM electron beam scans across the laser diode surface. Defects preventing laser diode radiation will be shown as contrast variations in the EBIL image. This technique is similar to electron beam induced current (EBIC), reference 1, in which the electron beam provides the capability for measuring subsurface electrical and physical parameters that effect device electrical performance. However in the case of EBIL, laser diode radiation is utilized as the imaging parameter providing direct correlation between the semiconductor active layer and the resultant diode luminescence output. Alternative techniques such as Cathode Luminescence (CL), reference 2 and 5, in the scanning electron microscope (SEM) have been used for examination of semiconductor laser diodes for defects preventing radiation. However CL SEM analysis requires costly accessories, including at least an ellipsoidal mirror and a cooled photomultiplier tube sensitive to the particular laser diode output frequency. In addition the laser diode must be at the focal point of an ellipsoidal mirror, making CL SEM examination of a packaged laser diode difficult or impossible. This paper will describe the EBIL technique using several test diodes to demonstrate the ability of EBIL to image diode luminescence and defects affecting luminescent output. Deprocessing of the laser diode top electrode and EBIL operating parameters will be discussed.
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