This study focuses on the development of high-speed adder circuits utilising the Hardware Description Language (HDL) within the Xilinx ISE 9.2i platform, as well as their implementation on Field Programmable Gate Arrays (FPGAs) to analyse planning parameters. The main building component of the Arithmetic Logic Unit (ALU) is the adder, and hence the performance of the Control Processing Unit is determined by it (CPU). The ALU and the register file are the two primary components of processors. The carry-chain extra operation could be one of the important channels within an ALU. In this paper, we've simulated and synthesised a variety of adders in order to find the most efficient one. Keywords: Adders, ALU, CPU, High speed adders, delay
In Digital Wireless Communication application, the design of Low Power and High Speed Analog to Digital Converter (ADC) is the nee d-of-the-day. This paper explores the design of low power and high s pee d comparator us e d in all available ADC architectures. The proposed architecture includes two stage CMOS Operational Amplifier (Op-Amp) circuit. The comparator described here is designed and implemented with 0.18µm technology operate d on 1Volt power supply using Cadence Virtuoso Tool. The functional verification of the comparator is carried out which in turn consumes 0.953 µW of power with propagation delay(s pee d) of 1.561ns. The overall improvement in the results in accordance with the literature is the s cope of this paper.
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