The flexibility of reconfigurable hardware can be exploited to adapt to requirements of applications while run-time. Hardware described functions can be configured dynamically when required, which leads to better usage of chip resources due to reduction of chip area and therefore reduced power consumption. Unfortunately the many restrictions of available run-time reconfigurable hardware architectures has until now limited the integration of such systems in real applications. Also, the high power consumption of reconfigurable architectures makes them suitable for mostly very high performance requiring applications such as signal processing tasks or multimedia applications. In this paper a method for 2D reconfiguration is described, which also enables on-line routing of communication primitives. In order to decrease the power consumption, we also propose a method for adapting signal routing according to power and performance. We demonstrate that there is a trade-off between the power and performance of on-chip signal lines, which can be exploited for on-line adaptation.
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