PECVD nitride passivated high-power PHEMT's were used to study their hot carrier reliability. The typical hot carrier induced device degradation characteristics are often observed in devices with a less-than-ideal double gate recess and material layers design. With additional drain engineering work to optimize device power performance, the hot carrier effects can be alleviated drastically. However, depending on nitride deposition processes and nitride quality, Schottky diode degradation (a barrier height increase) was also observed during hot carrier stress. This study facilitates a comprehensive characterization of the hot carrier induced effects in power PHEMT's and recommends an alternative to improve the hot carrier reliability.
Conventional wisdom suggests that in pseudomor-phic high electron mobility transistors (pHEMT's), the field between the drain and the gate determines off-state breakdown, and that the drain to gate voltage therefore sets the breakdown voltage of the device. Thus, the two terminal breakdown voltage is a widely used figure of merit, and most models for breakdown focus on the depletion region in the gate-drain gap, while altogether ignoring the source. We present extensive new measurements and simulations that demonstrate that for power pHEMT's, the electrostatic interaction of the source seriously degrades the device's gate-drain breakdown. We identify the key aspect ratio that controls the effect, L L LG G G : x x xD D D, where L L LG G G is the gate length and x x xD D D is the depletion region length on the drain. This work establishes that the design of the source must be taken into consideration in the engineering of high-power pHEMT's. Index Terms-Breakdown voltage, electric breakdown, electron tunneling, power HEMT's power MODFET's.
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