A low-jitter 110 MHz-to-620 MHz phase-locked loop (PLL) that includes a low-noise wide-frequency-range ring oscillator with a dual-mode operation is presented. The measurement results using a 65 nm low-power CMOS process show that the proposed PLL achieves as low as a 2.5 ps RMS jitter at 600 MHz of output frequency while consuming 2.7 mW at a 1.2 V supply. The die area is only 0.09 mm 2 .Introduction: Because of the increase in digital/analogue processing and communication systems and the tendency to integrate whole systems in a single chip, the demand for small-size, low-power phaselocked loops (PLLs) is increasing. The VCO (voltage-controlled oscillator) of the PLLs is the key block because its phase noise directly affects the quality of the output signal. Among diverse structures for the VCO realisation, a ring oscillator is attractive owing to its wide frequency range, low-voltage operation, multiple output phases generation, and easy integration in a standard CMOS process. However, ring oscillators generally show poor phase noise performance and high power consumption because of these low effective quality factors. To overcome these difficulties, several topologies have been proposed [1][2][3][4]. Nevertheless, the power dissipation is the critical issue in most cases. In this Letter, a small-size and low-power PLL is proposed by adopting a varactor-based low-noise ring-VCO.
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