Abstract:In this paper utilization of a buck-boost converter for control of photovoltaic power using Maximum Power Point Tracking (MPPT) control mechanism is presented. First the photovoltaic module is analyzed using MATLAB. For the main aim of the project is the buck -boost converter is to be used along with a Maximum Power Point Tracking control mechanism. The MPPT is responsible for extracting the maximum possible power from the photovoltaic and feed it to the load via the buck boost converter which steps up the voltage to required magnitude. The main aim will be to track the maximum power point of the photovoltaic module so that the maximum possible power can be extracted from the photovoltaic. The algorithms utilized for MPPT are generalized PO algorithms and are easy to model or use as a code. The algorithms are written in m files of MATLAB and utilized in simulation. Both the buck boost converter and the solar cell are modelled using Sim Power System blocks.
The urge of high performance and dynamic functionalities in an integrated circuit has led to aggressive technology scaling over the years. The supply voltage (V DD ), device threshold voltage (V th ) and the device geometry are expected to be scaled further with this trend. Which results in reducing the short channel effects and increased transistor OFF-state current (I OFF ). Additionally leakage currents, higher operating frequency and on die transistor count will lead to increase in total power dissipation. Dynamic logic technique is preferred over static logic technique for the higher performance circuit due to lesser delay which enhances the speed of the circuit and overall capacitance is low compare to CMOS which reduces the power consumption. In this paper we have calculate the Average power consumption and delay of various domino circuits provided with 8 input OR gate, comparison of power, delay, and Unit Noise Gain (UNG) of different topologies. The simulation is performed in HSPICE at 65nm and 45nm process technology with supply voltage 1V and 0.9V and operating temperature of 27⁰ C at 100 MHz for fair comparison of results. We have also calculated the power consumption and delay with the variation of keeper ratio in all the existing technique at 65nm and 45nm process technology.
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