This work proposes a novel methodology to evaluate SRAM-based FPGA's susceptibility with respect to Single-Event Upset (SEU) as a function of noise on VDD power pins, Total-Ionizing Dose (TID) and TID-imprinted effect on BlockRAM cells. The proposed procedure is demonstrated for SEU measurements on a Xilinx Spartan 3E FPGA operating in an 8 MV Pelletron accelerator for the SEU test with heavy-ions, whereas TID was deposited by means of a Shimadzu XRD-7000 X-ray diffractometer. In order to observe the TID-induced imprint effect inside the BlockRAM cells, a second SEU test with neutrons was performed with Americium/Beryllium ( 241 AmBe). The noise was injected into the power supply bus according to the IEC 61.000-4-29 standard and consisted of voltage dips with 16.67% and 25% of the FPGA's VDD at frequencies of 10 Hz and 5 kHz, respectively. At the end of the experiment, the combined SEU failure rate, given in error/bit.day, is calculated for the FPGA's BlockRAM cells. The combined failure rate is defined as the average SEU failure rate computed before and after exposition of the FPGA to the TID.
Ahstract-Nowadays, the major part of electronic devices make use of synchronous circuits controlled by a global clock signal. However, the noise sensitivity as well as the electromagnetic emission of this type of circuit is very high. In this context, asynchronous circuits represent a very interesting solution, since they are naturally more robust than the synchronous counterparts. The proposed work aims at comparing the robustness of synchronous and asynchronous circuits generated according to the Desynchronization Approach presented in III when they are exposed to power supply disturbances (PSD). To provide the necessary results to compare the two different design paradigms, we performed a set of experiments according to the IEC 61.000-4-17 and the IEC 61.000-4-29 Normatives 12,31. The obtained results demonstrate that the asynchronous circuit is significantly more robust than the synchronous one.
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