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This study investigates graded porosity in nanowire arrays to realize a new graded refractive index mechanism that results in unprecedented broadband antireflection and extends the photodetection properties to cover the entire visible-light range. In this work, ZnO nanowires (NWs) are chosen as a model system to demonstrate the porosity-induced antireflection and photodetection properties for visible light. Porous ZnO NW arrays (PZNA) were synthesized by the hydrothermal method followed by controlled hydrogen annealing for different durations. The surface pores of the PZNA were formed with a gradient distribution from the top to the bottom of the nanowires. This pore gradient distribution serves as a new mechanism to achieve a graded refractive index, which provides improved broadband antireflection in PZNA with a minimum reflectance of less than 5% at 800 nm. Moreover, the cathodoluminescence spectra suggest the evolution of many defects in PZNA, which contribute to defect-state excitation phenomena. Based on their unique features with regard to antireflection, multiple scattering and defect state excitation, the PZNA devices exhibit an exceptional capability for steady photodetection over the entire visible-light range. The corresponding unique photodetection mechanisms for the phenomena are discussed. These new physical phenomena can be readily extended to other 1D materials and used to develop other optoelectronic devices.

The geometry of solder joints in the flip chip technologies is primarily determined by the associated solder volume and die/substrate-side pad size. In this study, the effect of these parameters on the solder joint reliability of a fine-pitched flip chip ball grid array (FCBGA) package is extensively investigated through finite element (FE) modeling and experimental testing. To facilitate thermal cycling (TC) testing, a simplified FCBGA test vehicle with a very high pin counts (i.e., 2499 FC solder joints) is designed and fabricated. By the vehicle, three different structural designs of flip chip solder joints, each of which consists of a different combination of these design parameters, are involved in the investigation. Furthermore, the associated FE models are constructed based on the predicted geometry of solder joints using a force-balanced analytical approach. By way of the predicted solder joint geometry, a simple design rule is created for readily and qualitatively assessing the reliability performance of solder joints during the initial design stage.The validity of the FE modeling is extensively demonstrated through typical accelerated thermal cycling (ATC) testing. To facilitate the testing, a daisy chain circuit is designed, and fabricated in the package for electrical resistance measurement. Finally, based on the validated FE modeling, parametric design of solder joint reliability is performed associated with a variety of die-side pad sizes. The results show that both the die/substrate-side pad size and underfill do play a significant role in solder joint reliability. The derived results demonstrate the applicability and validity of the proposed simple design rule. It is more surprising to find that the effect of the contact angle in flip chip solder joint reliability is less significant as compared to that of the standoff height when the underfill is included in the package.

Gallium nitride p-i-n ultraviolet photodiodes with low-temperature (LT)-GaN interlayer have been fabricated. It was found that the dark current of photodiode with LT-GaN interlayer is as small as 143pA at 5V reverse bias. It was also found that the responsivity of the photodiode with LT-GaN interlayer can be enhanced at a small electric field (∼0.4MV∕cm) due to the carrier multiplication effect. The UV photocurrent gain of 13 and large ionization coefficient (α=3.1×105cm−1) were also observed in the detector with LT-GaN interlayer. Furthermore, we can achieve a large peak responsivity of 2.27A∕W from the photodiode with LT-GaN interlayer.