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The S-box is a basic important component in symmetric key encryption, used in block ciphers to confuse or hide the relationship between the plaintext and the ciphertext. In this paper a way to develop the transformation of an input of the S-box specified in AES encryption system through an artificial neural network and the multiplicative inverse in Galois Field is presented. With this implementation more security is achieved since the values of the S-box remain hidden and the inverse table serves as a distractor since it would appear to be the complete S-box. This is implemented on MATLAB and HSPICE using a network of perceptron neurons with a hidden layer and null error.

In this paper, we present a teaching methodology based on a low‐cost embedded system platform that is easy to use and replicate, oriented to real‐time simulation project development. Designed for real‐time implementation of coding generated with MPLAB Device Blocks for Simulink. The purpose of this methodology is that students, teachers, and professionals will be able to carry out a theoretical project of a simulation in a computer, which includes complex mathematical modeling, to interact with its environment in real‐time. This system has been utilized already by students of Engineering of the first semesters as well as professors and researchers in updated and initialization courses in embedded systems within the University of Guadalajara. Finally, in the results section, we show a comparison of the proposed platform and a dSPACE platform applied in a control problem with an intricate mathematical model to process through a Hardware‐in‐the‐loop (HIL).

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This paper presents the design, implementation, and experimental results of 32-bit asynchronous microprocessor developed in a synchronous reconfigurable device (FPGA), taking advantage of a hard macro. It has support for floating point operations, such as addition, subtraction, and multiplication, and is based on the IEEE 754-2008 standard with 32-bit simple precision. This work describes the different blocks of the microprocessors as delay modules, needed to implement a Self-Timed (ST) protocol in a synchronous system, and the operational analysis of the asynchronous central unit, according to the developed occupations and speeds. The ST control is based on a micropipeline used as a centralized generator of activation signals that permit the performance of the operations in the microprocessor without the need of a global clock. This work compares the asynchronous microprocessor with a synchronous version. The parameters evaluated are power consumption, area, and speed. Both circuits were designed and implemented in an FPGA Virtex 5. The performance obtained was 4 MIPS for the asynchronous microprocessor against 1.6 MIPS for the synchronous.