The constant pursuit of low-cost Smart Environmental Monitoring Systems (SEMS) leads to a constant use of off the shelf sensors and components. However, with a lack of validation and calibration of the sensors, the accuracy of the measurements should be question. Especially when it comes to the monitoring of living environments such as homes, offices, and classrooms, where individuals remain for extended periods of time, and where prolonged exposure to hazardous environments can lead to health problems and discomfort. The objective of this research is to shine the light on a constantly overlooked parameter, the accuracy of the measurements taken by SEMS. In particular, the presented research focuses on the measurement science point of view giving a comparison of the most widely utilized sensors for living environment monitoring and the accuracy that can be expected from them. The final aim is, in on one end, to stimulate the research in the field to define the desired accuracy in the different applicative sectors, and on the other end, to increase the awareness of both producers and consumers about the metrological aspects of the sensors they produce/use and of the overall monitoring systems.
This work focuses on several synthetizations developed in both 32nm and 500nm technologies to evaluate the performance differences of MD5 Crypto-Processor. We decided to conduct a topographical synthesis instead of a nontopographical synthesis as it takes more parameters into account to create a more accurate design. We started by comparing some basic cells like inverters and register banks to understand the main differences between the two technologies. Several approaches were considered at this point to understand how different synthetization parameters affect the chip performance and characteristics. These different approaches were focused on time, power and area, and balanced configurations of synthesis flow. Finally, after comparing the performance given by the different approaches in basic digital structures, the balanced approach was implemented in 32nm and benchmarked with the 500nm implementation. Our conclusions were consistent among the various tests conducted and by downscaling we can expect a 10x increase in the clock frequency, a 100x decrease in power consumption, and around a 300x decrease in the area while using the 32nm technology. As a result, we developed a method to fairly compare complex systems to allow a designer to consider if the benefits justify the costs for a technology change.
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