Because the leakage current of a digital circuit depends on the states of its logic gates, assigning a minimum leakage vector (MLV) to the primary inputs and the flip-flops' output pins of the circuit that operates in the sleep mode is a feasible technique for leakage current reduction. In this paper, we propose a novel probability-based algorithm and technique that can rapidly find an MLV. Unlike most traditional techniques that ignore the leakage current overhead of the newborn MLV controller, our technique can take this overhead into account. Ignoring this overhead during solution exploration may bring a side effect that is misrecognizing a non-optimum solution as an optimum one. Experimental results show that our algorithm can reduce the leakage current up to 48% and can find the optimum solutions on 22 out of 26 small MCNC benchmark circuits.
Power-gating is an effective approach for reducing both dynamic and static power dissipation in power management Power Power-up (D) Shut-do-n(D) and test scheduling. This paper formulates the power-gating spike A ! = problem, derives a reduced power dissipation model as heuristics, proposes a vector control technique for post-gating circuits, and A C develops a sleep-transistor allocation scheme for power-on/off current spikes reduction of pre-gating systems. From experimental results, a justified controlling vector can reduce the on/off peak power up to 55%. For a pre-gating system, more than 83%Test time of the power-gating spike can be reduced. From our preliminary Fig. 1 A power-gating problem during scheduling. simulations using HSPICE so far, this heuristics has been proved to reduce the supply-gating current spike.In [9], the authors assume that the power-up charging current is proportional to the total charge for all load capacitance.
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