In this paper we describe the simulator FASTNR (FAST Newton-Raphson) where an efficient methodology for solving the faulty circuit equations, called FAult RUBber Stamps (FARUBS), is implemented. Its application to single fault simulation in linear and nonlinear circuits is reported. The efficient fault simulation in nonlinear DC circuits is due both to the development of original linearized Newton-Raphson models for electronic devices and to the simulation of fault values in a "continuation" stream. Fault simulation in linear cascades with up to 5000 nodes has shown an improvement of four orders of magnitude in simulation time, when compared to that of the nominal circuit. In nonlinear circuits, the time efficiency is sometimes better than two orders of magnitude.
The MiniPET project aims to design and build a small PET system. It consists of two 4×4 matrices of 16 LYSO scintillator crystals and two PMTs with 16 channels resulting in a low cost system with the essential functionality of a clinical PET instrument. It is designed to illustrate the physics of the PET technique and to provide a didactic platform for the training of students and nuclear imaging professionals as well as for scientific outreach. The PET modules can be configured to test for the coincidence of 511 keV gamma rays. The model has a flexible mechanical setup [1] and can simulate 14 diferent ring geometries, from a configuration with as few as 18 detectors per ring (ring radius φ =51 mm), up to a geometry with 70 detectors per ring (φ =200 mm). A second version of the electronic system [2] allowed measurement and recording of the energy deposited in 4 detector channels 4 by photons from a 137 Cs radioactive source and by photons resulting of the annihilation of positrons from a 22 Na radioactive source. These energy spectra are used for detector performance studies, as well as angular dependency studies. In this paper, the mechanical setup, the front-end high-speed analog electronics, the digital acquisition and control electronics implemented in a FPGA, as well as the data-transfer interface between the FPGA board and a host PC are described. Recent preliminary results obtained with the 4 active channels in the prototype are also presented.
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