This article presents an efficiency enhanced CMOS power amplifier using a digitally controlled dynamic bias switching method. It is composed of a dynamic bias switching circuit and a power amplifier circuit. The control signal for bias switching operation is generated by the digital signal processing unit according to the amplitude of the envelope signal. Then, the dynamic bias switching circuit offers two different supply voltages to the drain of the power amplifier. The low supply voltage is generated by a DC–DC converter within the dynamic bias switching circuit, while the high voltage can be directly supplied by the battery. The threshold voltage for the envelope signal and the low supply voltage level were analytically optimized for maximum efficiency enhancement using the envelope statistics of the LTE signal. The gain difference between low and high bias voltage conditions was compensated for better linearity of the power amplifier. The proposed dynamic bias and power amplifier IC's were designed and fabricated using 0.18 μm CMOS process. The fabricated CMOS power amplifier IC using the dynamic bias switching method was evaluated using a 64 QAM LTE up‐link signal which has a center frequency of 1.75 GHz, a signal bandwidth of 5 MHz, and a peak‐to‐average power ratio of 7.76 dB. It exhibited a power‐added efficiency of 39.3% and an error vector magnitude of 4.6% at an average output power of 22 dBm, while the stand‐alone CMOS power amplifier has an efficiency of 34.5%. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:2315–2321, 2015
A dual‐mode supply modulator is presented for a complementary metal‐oxide semiconductor envelope tracking power amplifier (PA) integrated circuit. The proposed supply modulator, based on a hybrid buck converter, has dual Class‐AB buffers and dual switches for the linear and switching amplifiers, respectively. For high average output power levels [or high‐power mode (HPM)], the supply modulator is controlled to have full sizes for both the buffer and switch to supply peak envelope voltage and high output current to the PA. The supply modulator is reconfigured to have smaller sized Class‐AB buffer and switch for low average output power levels (or low‐power mode). The smaller sized buffer and switch are used to reduce the quiescent current of the linear amplifier and to maintain high efficiency of the switching amplifier for a lightly loaded condition. For the 16‐QAM LTE uplink signal with a channel bandwidth of 5 MHz, the PA with the proposed supply modulator delivered a power‐added efficiency of 46.2% at an average output power of 24 dBm for a high power mode, which shows an improvement of 8.0% compared to the stand‐alone PA. For a low power mode, the PA with a reconfigured supply modulator has a power‐added efficiency of 12% at an output power of 9 dBm, which is a back‐off of 15 dB. This is 1.6 and 7.2% higher than that using the supply modulator for the HPM and for the stand‐alone PA at the same output power, respectively. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:1338–1343, 2015
Abstract-This paper presents a dual-mode bias modulator (BM) for complementary metal oxide semiconductor (CMOS) power amplifiers (PAs). The BM includes a hybrid buck converter and a normal buck converter for an envelope tracking (ET) mode for high output power and for an average power tracking (APT) mode for low output power, respectively. The dual-mode BM and CMOS PA are designed using a 0.18-mm CMOS process for the 1.75 GHz band. For the 16-QAM LTE signal with a peakto-average power ratio of 7.3 dB and a bandwidth of 5 MHz, the PA with the ET mode exhibited a poweradded efficiency (PAE) of 39.2%, an EVM of 4.8%, a gain of 19.0 dB, and an adjacent channel leakage power ratio of -30 dBc at an average output power of 22 dBm, while the stand-alone PA has a PAE of 8% lower at the same condition. The PA with APT mode has a PAE of 21.3%, which is an improvement of 13.4% from that of the stand-alone PA at an output power of 13 dBm.
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