A bottom-up approach was the key to the successful fabrication of this memory. This approach both minimized the number of processing steps following deposition of the molecular monolayer, as well as protected the molecules from remaining processing steps. In the following paragraphs, we briefly describe the nanofabrication procedures utilized to construct the memory circuit. A full paper describing these procedures in more detail will be submitted for publication in the near future. form an array of top Ti NW electrodes, and the crossbar structure is complete.

A demultiplexer is an electronic circuit designed to separate two or more combined signals. We report on a demultiplexer architecture for bridging from the submicrometer dimensions of lithographic patterning to the nanometer-scale dimensions that can be achieved through nanofabrication methods for the selective addressing of ultrahigh-density nanowire circuits. Order log 2 ( N ) large wires are required to address N nanowires, and the demultiplexer architecture is tolerant of low-precision manufacturing. This concept is experimentally demonstrated on submicrometer wires and on an array of 150 silicon nanowires patterned at nanowire widths of 13 nanometers and a pitch of 34 nanometers.

High density metal cross bars at 17 nm half-pitch were fabricated by nanoimprint lithography. Utilizing the superlattice nanowire pattern transfer technique, a 300-layer GaAs/AlGaAs superlattice was employed to produce an array of 150 Si nanowires (15 nm wide at 34 nm pitch) as an imprinting mold. A successful reproduction of the Si nanowire pattern was demonstrated. Furthermore, a cross-bar platinum nanowire array with a cell density of approximately 100 Gbit/cm(2) was fabricated by two consecutive imprinting processes.

Supplemental Information: Detailed Experimental Methods Impurity DopingSi(111) SOI wafers were diced into 1 cm 2 pieces, and the individual chips were sonicated in methanol and gently swabbed using a Texwipe CleanTip swab to remove particulates. (Note that the parent wafer was free from organic contamination since it underwent iterations of oxidation followed by BOE-etching to thin the Si(111) SOI epilayer.) After ensuring the wafer was free from particulates, as determined by inspection using an optical microscope at 160x magnification, a 1:10 diluted (dopant to methanol) spin-on dopant solution was spin-coated (at 4000 RPM) onto the wafer surface and subsequently baked at 200° C for 10 min to drive off excess solvent. Emulsitone (Whippany, NJ) Phosphorosilicafilm and Borosilicafilm were used for n-type and p-type doping, respectively. The dopant-film-coated wafer was then annealed under nitrogen in a rapid thermal annealer for the appropriate time and temperature to achieve a given impurity dopant concentration. The dopant film was removed by swirling the chip in BOE until the surface became hydrophobic, and surface resistivity measurements using four-point probe techniques where immediately taken. The doping was easily determined from resistivity measurements through the use of an empirical relation giving dopant density as a function of resistivity. 35,43 Dopant density vs. depth measurements were obtained by iterating four-point probe resistance measurements with CF 4 -based reactive-ion etching of the Si surface to remove

The electrical characteristics of Si nanowire gated by an array of very closely spaced nanowire gate electrodes are experimentally determined and theoretically modeled. Qualitative and quantitative changes in the transport characteristics of these devices, as a function of gate-array voltage, are described. Experiments are reported for two widths of Si nanowires, 40 and 17 nm, and for a varying number of gate electrodes, all spaced at a pitch of 33 nm. We find that these top nanowire gate electrodes can be utilized to locally deplete the carriers in the underlying Si nanowire and thus define an array of coupled quantum dots along the nanowire. Reproducible Coulomb blockade is observed, and clear diamond features are obtained when the conductance is plotted in the plane of the source-drain and gate voltages. The regularity of the diamond diagrams is imposed by the regularity of the SNAP top gate electrodes. Model computations of the electronic structure starting from a tight-biding Hamiltonian in the atomic basis suggest that the control made possible by the top gate voltage induces the emergence (and reversible submergence) of a coupled quantum dot structure in an otherwise homogenously doped Si nanowire.