The High-Speed Optoelectronic Memory Systems (HOLMS) project, sponsored by the European Union Information Society Technology program, aims to make the use of board level optical interconnection in information systems practical and economical by developing optoelectronic packaging technology compatible with standard electronic assembly processes. To demonstrate the potential of the technology, it develops a demonstrator system that addresses the most pressing problem of contemporary computer architecture: memory latency. This paper describes the key ideas and some preliminary results of the HOLMS projects focusing on the electronic interconnection technology, in particular optoelectronic packaging issues.
The high-speed optoelectronic memory system project is concerned with the reduction of latency within multiprocessor computer systems (a key problem) by the use of optoelectronics and associated packaging technologies. System demonstrators have been constructed to enable the evaluation of the technologies in terms of manufacturability. The system combines fiber, free space, and planar integrated optical waveguide technologies to augment the electronic memory and the processor components. Modeling and simulation techniques were developed toward the analysis and design of board-integrated waveguide transmission characteristics and optical interfacing. We describe the fabrication, assembly, and simulation of the major components within the system.
A novel, to our knowledge, type of packet scheduler that could significantly outperform current state-of-the-art schedulers is presented. The operation and the design of such a scheduler are discussed, and a fully operational experimental implementation is described. The scheduler uses a neural network in a winner-take-all strategy to optimize decisions on the throughput of both a crossbar and a banyan switching fabric. The problems of high interconnection density are solved by use of a free-space optical interconnect that exploits diffractive optical techniques to generate the required interconnection patterns and weights.
An optoelectronic neural network is presented that is designed to solve the assignment problem--or any similar optimization task given minimal adjustment--in both crossbar and banyan packet switches. We examine the design decisions made at the hardware, software, and algorithmic levels and indicate the associated effect on the system as a whole. Clearly detailed experimental results show the system's robustness and performance due to the particular optoelectronic-algorithm combination used. The integration and packaging of such a system are also briefly discussed.
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