The development of a CCD -based parallel analog processor is described. The singleinstruction, multiple -data (SIMD) architecture allows substantial throughput improvements when compared to conventional serial image processing hardware.The heart of the concept is a single -chip array of analog processing elements interconnected with a two -dimensional CCD shift register network. The same analog operation is performed on all cells simultaneously.The device shows great promise in medium resolution (100 x 100) applications (such as guided weapons and robotics) where it can be directly interfaced with a staring focal plane through bump interconnections.A 16 x 16 test chip has been built with the processing elements on 10 -mil centers. Leakage current, charge transfer efficiency, and uniformity measurements on this chip indicate a level of performance typical of more conventional CCDs. A cell with increased storage and arithmetic capabilities has been designed. This new cell contains six dedicated charge storage sites arranged in a ring. The cell also contains a multiplier/ regenerator circuit, a random -access output, and is compatible with sensor inputs from a fully -parallel array.The hierarchy of software developed for the parallel analog processor allows it to perform target detection, recognition, and classification funtions.FLIR images of tanks were processed by the parallel analog processor using simple threshold, edge, and contrast enhancement routines and the results are presented.Background
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