No abstract

A novel direct resistive-sensor-to-digital readout circuit is presented that achieves 16.1-bit ENOB while being very compact and robust. The highly-digital time-based architecture employs a single VCO, counter and digital feedback loop for the read-out of an external single-ended highly-nonlinear resistive sensor such as a NTC thermistor. In addition to the inherent 1 st -order noise shaping due to the oscillator, a second loop in SMASH configuration creates 2 nd -order noise shaping. Fabricated in 180nm CMOS, the readout circuit achieves 16.1 bit of resolution for 1ms conversion time and consumes only 171µW, resulting in an excellent 2.4pJ/c.s. FOMW for a resistive sensor interface, while occupying only 0.064mm 2 . The specific closedloop architecture tackles the VCO nonlinearity, achieving more than 14 bits of linearity. Multiple prototype chip samples have been measured in a temperature-controlled environment from −40 • C to 125 • C for the readout of commercial external NTC thermistors. A maximum temperature inaccuracy of 0.3 • C is achieved with only 1-point trimming at room temperature. Since the circuit architecture decouples the sensor excitation from the feedback, high EMI immunity at the sensor node is demonstrated as well.

This paper presents the theoretical and comparative analysis of two major time-based architectures for sensor interfaces. Both use a voltage-controlled oscillator (VCO) to achieve a highly-digital scalable implementation. The first architecture is based on a phase-locked loop, while the second one is countbased. Both systems are closed loop to efficiently mitigate the VCO nonlinearity. They show inherent first-order quantization noise shaping thanks to the use of an oscillator and phase detection. The two systems having a different working principle leads to different VCO requirements in terms of gain linearity (V-to-f or V-toT linearity). Formulas are derived to predict the maximum SQNR for both architectures. Equations for the achievable maximum SNR taking into account the VCO phase noise are also derived, since this is the limit to the SNR in practical implementations. State-variable-based simulation results are presented, confirming the theoretical analysis and emphasizing the different design trade-offs and practical considerations.

No abstract

Due to their high compatibility with scaled CMOS and emerging technologies, highly-digital time-based architectures, such as PLL-based architectures, have become an attractive alternative to amplitude-based circuits for sensor interfaces, in terms of high time resolution and the potential for low power and area scalability. Although quantization and thermal noise in PLL-based architectures can be addressed by applying noise shaping and oversampling, offset and 1/f noise limit the resolution at high oversampling ratios. Therefore, dynamic offset cancellation techniques such as chopping and autozeroing, as used in traditional amplitude-based circuits, must be adapted to such time-based implementations as well. This paper presents a digital-domain chopping technique suited for offset and 1/f-noise cancellation in applications where medium-tohigh-resolution sensor interfaces are needed. System-level simulations demonstrate the benefits of this technique at high oversampling ratios. The resolution improvement is confirmed by measurements, showing the rate of 10dB of SNR gain per decade of oversampling as expected from theory.