As the design rule of device shrinks down, it is difficult to enlarge the process window, especially DOF (Depth of Focus). It has shown good results in resolution issues with short wavelength, high NA aperture and several RET (Resolution Enhancement Technique) like special illuminator and mask techniques and so on. But it needs to be challenged for DOF process window in contact / via process having various pitch and pattern location. It is a key point in sub 100nm process development and product. It is demonstrated that focus scan method is effective for DOF improvement in contact and via layers. Focus Scan method is one of the focus drilling techniques; it is realized to tilt wafer stage so that the same point on the wafer field can be exposed in limited continual focus range using multiple focal planes through the slit of scanner tool. In this study, confirmation was inspected for simulation and wafer evaluation for focus scan effects in view of process feasibility. DOF increased over 50% with focus scan in contact mask process even though there are several issues to be solved and considered. Energy Latitude (EL) decreased a little by image contrast drop, but if we consider the process window for evolution of device, it is relatively enough for process. OPC or Bias tuning is needed for application in contact layer having various pitch and location, and overlay issues are needed to confirm for each illuminator. From these experiments, it is found that DOF margin can easily be enhanced using focus scan method. Also some fine tuning is required to adequately use this method on production devices.
The study of OPC (Optical Proximity Correction) model that well predict the wafer result has been researched. As the pattern design shrink down, the need for the CD (Critical Dimension) controllability increased more than before. To achieve these requirements, OPC models must be accurate for full chip process and model inaccuracies are one of several factors which contribute to errors in the final wafer image. For that reason, robust OPC using real lithographic terms was proposed. Real lithographic system is quite different from ideal system that is used for OPC modeling. Until now, this difference was acceptable since pattern size used for OPC model was large, but as device size shrinks, this gap between ideal and real system causes degradation of OPC accuracy. So, various optical parameters such as apodization, laser band width, degree of polarization, illumination are used today in order to compensate for this issue. Especially, major issue in modeling error is related to how the illumination source is used.For this study we assess accuracy of optical model for robust OPC using ideal and actual illumination sources, and test conditions are below. 1) We examined the difference of pupil types to output model respectively.2) A parameterized test pattern layout was used by 1D test pattern types that have various lines and spaces. 3) All models were calculated in automation method so as to exclude the dependency of user skills. 4) OPC accuracies were examined by gate layer patterns on full chip level. The study is performed for 5X~4Xnm nodes lithographic processes. The main focus of the study was on usability of model that is made by measured source data in semiconductor manufacturing. Results clearly showed that the actual source for the optical model has merits and demerits.
It is necessary to apply extreme illumination condition on real device as minimum feature size of the device shrinks. As k1 decrease, ultra extreme illumination has to be used. However, in case of using this illumination, CD and process windows dramatically fluctuate as pupil shapes slightly changes. For past several years, Pupil Fit Modeling (PFM) was developed in order to analyze pupil shape parameters which are independent from each others. The first object in this work is to distinguish pupil shape of different scanner by separating more parameters. According to pupil parameter analysis, the major factors of CD or process window difference between two scanner systems obviously appear. Due to correlation between pupil parameter and scanner knob, pupil parameter analysis would be clearly identified which scanner knob should be compensated. The second object is to define specification of each parameter by using analysis of CD budget for each pupil parameters. Using periodic monitoring of pupil parameter which is controlled by previous specification, scanner system in product lines can be maintained at ideal state. Additionally, OPC model accuracy enhancement should be obtained by using highly accurate fitted pupil model. Recently, other application of pupil model is reported for improvement of OPC and model based verification model accuracy. Such as modeling using average optics and hot spot detection of scanner specific model are easily adopted by using pupil fit model. Therefore, applications of pupil fit parameter for process model are very useful for improvement of model accuracy.In our study, the quantity of model accuracy enhancement using PFM is investigated and analyzed. OPC and hotspot point detection capability results with pupil fit model would be shown. Also, in this paper, trends of CD and process window for each scanner parameter are evaluated by using pupil fit model. As of results, we were able to find which pupil parameter has influence in critical layer CD and application of this result resulted in better accuracy in detecting hotspot for model based verification.
As the industry pushes to ever more complex illumination schemes to increase resolution for next generation memory and logic circuits; subresolution assist feature (SRAF) placement requirements become increasingly severe. Therefore device manufacturers are evaluating improvements in SRAF placement algorithms which do not sacrifice main feature (MF) patterning capability. AF placement algorithms can be categorized broadly as either rule-based (RB), model-based (MB). However, combining these different algorithms into new integrated solutions may enable a more optimal overall solution.RBAF is the baseline AF placement method for many previous technology nodes. Although RBAF algorithm complexity limits its use with very extreme illumination, RBAF is still a powerful option in certain scenarios. One example is for repeating patterns in memory arrays. RBAF algorithms can be finely optimized and verified experimentally without the building of complex models. RBAF also guarantees AF placement consistency based only on the very local geometric environment, which is important in applications where consistent signal propagation is of critical importance.MBAF algorithms deliver the ability to reliably place assist features for enhanced process window control across a wide variety of layout feature configurations and aggressive illumination sources. These methods optimize sophisticated AF placement to improve main feature PW but without performing full main feature OPC. The flexibility of MBAF allows for efficient investigations of future technology nodes as the number of interactions between local layout features increases beyond what RBAF algorithms can effectively support Based on hybrid approach algorithms combining features of the different algorithms using both RBAF and MBAF methods, the generation and placement of SRAF can be a good alternative. Combining of two kinds of SRAF placement options might result in relatively improved process window compared to an independent approach since two methods are capable of supplement each other with a complementary advantages.In this paper we evaluate the impact of SRAF configuration to pattern profile as well as CD margin window and manufacturing applications of MBAF and Hybrid approach algorithms compared to the current OPC without AF. As a conclusion, we suggest methodology to set up optimum SRAF configuration using these AF methods with regard to process window.
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