In the present study, moisture and temperature distributions and residual stresses in plastic encapsulated integrated circuit (IC) packages are evaluated in order to assess product reliability. Finite element analyses are utilized to calculate hygro-thermally induced deformations and stresses in plastic IC packages during the surface mounting process preceded by the moisture soaking test. Residual stresses developed in thin lead-onchip (LOC) thin small outline packages (TSOP) packages during the reflow soldering process preceded by the 168 h 85 C/85% RH moisture soaking test have been studied. Numerical results showed that substantially high positive stresses z arose in the silicon chip and the leadframe while negative stresses were observed in the encapsulant below the chip when TSOP packages were exposed to the reflow soldering process. Such opposite stress development in the silicon chip and encapsulant below the chip may result in the delamination and popcorn crack. The results also showed that the magnitude of residual stresses in IC packages depended not only on the magnitude of loading but also on the loading history due to the hygro-thermo-viscoelastic behavior of plastic mold compound materials.Index Terms-Effects of moisture and temperature on plastic IC packages, hygro-thermo-viscoelastic analysis, TSOP, time dependent deformations and stresses and failures.
In the present study, the moisture and temperature distributions and residual stresses inside plastic encapsulated IC packages are evaluated in order to asses product reliability. Numerical procedures based on finite element analyses are presented to calculate the hygro-thermally induced deformations and stresses in plastic IC packages during the surface mounting process preceded by the moisture soaking test. For example, residual stresses in thin LOC (Lead-On-Chip) TSOP packages during the reflow soldering process preceded by the 168 hours 85 "C/ 85% RH moisture soaking test have been studied. Numerical results show that when TSOP packages undergo the reflow soldering process substantially high tensile CT= stresses arose in the silicon chip while high compressive stresses were in the encapsulant below the chip. Such high compressive and tensile stress development in the silicon chip and encapsulant below the chip is responsible for the delamination and popcorn crack. The results also show that the magnitudes of residual stresses in IC packages may depend not only on the magnitude of loading but also on the loading history due to the hygro-thermoviscoelastic behavior of plastic mold compound materials.
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