An optical analog can be constructed for the diffraction of low-energy electrons from a single-crystal surface covered with a layer of adsorbed molecules. The project is of appropriate difficulty and duration for an undergraduate student project and the results can yield insight into current research problems. The optical simulation of low-energy electron diffraction patterns also makes an effective classroom demonstration for introducing the concept of the wave nature of particles.
The experimental methodology to characterize the nanoscale local lattice strain in advanced Si CMOS devices by using Focused Ion Beam (FIB) system and Convergent Beam Electron Diffraction (CBED) is discussed. Through both high spatial resolution of Transmission Electron Microscopy (TEM) and high strain sensitivity of the CBED technique, compressive lattice strains in the order of 10 -3 from the nanoscale Si PMOS channel region are detected. The one-dimensional quantitative strain-mapping is performed by obtaining and simulating high quality CBED patterns with different zone axes such as <230> and <340>.
One of the major issues of concern with the scaling down of the IC size is the stress built up in the active layers of advanced Si CMOS devices, which affects the device performance [1]. Conventional lattice strain measurements using micro-Raman spectroscopy [2] or x-ray diffraction [3] could not be used due to the lack of spatial resolution needed for the characterization of nanoscale devices. The TEM/CBED method is a powerful method for measuring local lattice strains due to its high spatial resolution and sensitivity. In this paper, we present results on the nanoscale local lattice strains measured from a Si PMOS transistor at a 37 nm gate length.A recessed SiGe epitaxial layer was used to compressively strain the PMOS. A detailed process flow is described elsewhere [4]. Fig. 1 is a cross-sectional TEM image, showing a 37nm gate PMOS with SiGe integrated at the drain extension (DE). This local strain approach is expected to improve the hole mobility. Site-specific TEM samples were prepared by FIB. The thickness of the TEM sample chosen for CBED analysis at 200 kV was approximately 200 nm. Low power plasma cleaning was applied to remove the surface contamination. A JEMS software package was used to simulate High Order Laue Zone (HOLZ) line patterns [5].The CBED patterns were taken in the <230> zone axis (which is 11.3° off the <110> orientation) at 200 kV from the locations marked in Fig. 1(a). Fig. 1(b) is a CBED pattern taken from a region of the sample which is unstrained. The "effective" voltage was found by comparing the experimental and simulated ones. This "effective" voltage, which was found be 200.37 kV, was used to analyze the patterns taken from the strained region ( Fig. 1(c)). A compressive strain of approximately 0.209% was found in this region, as expected in this device. However, the accuracy of the measurements suffered from the blurring of the pattern. This can be attributed to the nonhomogeneous strain in the analyzed volume, the surface relaxation, or the thermal diffuse scattering. A Gatan Imaging Filter (GIF) was used to improve the quality of CBED patterns. Fig. 2 shows room temperature energy-filtered CBED patterns. The improvements due to energy-filtering are clearly observed. A new set of CBED patterns (energy-filtered) was taken from the locations marked in Fig. 1(a). The strain analysis indicated a compressive strain gradient that decays from the center channel region, as predicted by ANSYS based stress simulations. In conclusions, we have successfully analyzed local lattice strains by CBED from the channel regions in a Si CMOS device with a gate length as small as 37 nm. A new choice of zone axis such as <560>, which is 5.2° off the <110> orientation, is also being explored in order to minimize the specimen-tilt projection effect, and the results will be discussed [6].
This paper presents two case studies, based on 32nm Silicon-On-Insulator (SOI) and 28nm bulk Si technology, on finding the root cause of nanometer scale short failures using Passive Voltage Contrast (PVC), Active Voltage Contrast (AVC) and Transmission Electron Microscopy (TEM). PVC/AVC is used as precision localization technique that is critical for a successful FA-TEM analysis. Combining planar TEM sample preparation and high sensitivity Energy Dispersive Spectroscopy (EDS) mapping, a small residual filament, which is not visible even at high resolution TEM, is found to short two metal lines. The effective usage of voltage contrast and TEM provides the need of high throughput, high precision, and high resolution in the advanced FA lab that serves leading-edge semiconductor manufacturing.
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