The growth of battery-powered mobile and wearable devices has increased the importance of low-power operation and cost in system-on-a-chip (SoC) design. Supply-voltage scaling is the predominant approach to active power reduction for SoC design, including voltage scaling for on-die memory given increasing levels of memory integration. SRAM can limit the minimum operating voltage (V MIN ) of a design, often leading to the introduction of separate voltage supplies for on-die memory. Additional supplies increase platform cost, and operating memory at higher voltage leads to increased power consumption. The introduction of trigate devices at the 22nm technology node delivered superior short channel effects and subthreshold slope relative to existing bulk planar device technology enabling reduction in threshold voltage within a fixed leakage constraint. Lower transistor V th , improvements to random device variability, and assist circuits to overcome device-size quantization enabled a >150mV reduction in SRAM V MIN [1]. At the 14nm technology node, FinFET device-size quantization remains a challenge for compact 6T SRAM bitcells with minimum-size transistors. Careful co-optimization between technology and design of memory-assist circuits is required in order to deliver dense, low-power memory operation at low voltages. In this paper, we present an 84Mb SRAM array design with wide-voltage-range operation in a 14nm logic technology featuring 2 nd -generation FinFET transistors. Figure 17.1.1 shows a layout diagram of a 0.0500μm 2 high-density 6T SRAM cell (HDC) and a 0.0588μm 2 low voltage 6T SRAM cell (LVC) in 14nm FinFET technology [2]. HDC has a fin ratio of 1:1:1 (PU:PG:PD) and LVC features a larger PD device at 1:1:2, to provide improved read stability and performance at low voltage. Self-aligned double-patterning techniques have extended the capabilities of 193nm immersion lithography on critical layers to deliver 0.54× scaling relative to comparable 22nm SRAM bitcells. Contacted gate pitch is 70nm and fin pitch is 42nm for the technology. Figure 17.1.1 highlights recently reported SRAM designs from 16nm, 14nm and 10nm technologies [1-6]. The 0.050μm 2 HDC cell in this work is the smallest reported SRAM cell at any technology node among the cited work. Despite significant geometric scaling from the 22nm node, optimizations to fin profile and subfin doping on the 2 nd -generation FinFETs enable a nearly 2× reduction in device random threshold voltage variation [2], a critical factor for 6T SRAM V MIN .The HDC SRAM cell has a 1:1 PG to PD ratio, leading to degraded stability from charge injection during read operations. Wordline underdrive (WLUD) is utilized in the HDC arrays as an area-efficient approach to enhance read-stability margin at the cost of cell performance [1]. Suppressed BL techniques, such as the DNR circuit, also improve read stability, but are effective across a limited range of process technology targets and the implementation leads to more area overhead and higher power consumption than WLUD [3]. T...

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