This paper presents a multilevel inverter topology suitable for the generation of dodecagonal space vectors instead of hexagonal space vectors as in the case of conventional schemes. This feature eliminates all the 6n ± 1 (n = odd) harmonics from the phase voltages and currents in the entire modulation range with an increase in the linear modulation range. The topology is realized by flying capacitor-based three-level inverters feeding from two ends of an open-end winding induction motor with asymmetric dc links. The flying capacitor voltages are tightly controlled throughout the modulation range using redundant switching states for any load power factor. A simple and fast carrier-based space-vector pulsewidth modulation (PWM) scheme is also proposed for the topology which utilizes only the sampled amplitudes of the reference wave for the PWM timing computation. Index Terms-Dodecagonal space vectors, flying capacitor, multilevel inverters, open-end winding, space-vector pulsewidth modulation (PWM).
Single stage LLC resonant converters with inherent power factor correction are getting popularity in AC-DC converters due to its reduced size and weight. However, single stage topologies are usually less efficient in regulating the dc bus capacitor voltage pertaining to line and load transients. This paper proposes a multi-level flying capacitor based single stage AC-DC LLC topology to address the issue of voltage balancing of dc-bus capacitor and to reduce the voltage stress of the switching devices. The proposed three-level inverter topology guarantees zero voltage switching, less circulating currents, reduced switching stress and losses. The converter uses bridgeless rectification scheme for better efficiency and the power factor is made nearly unity by operating the source-side inductor in discontinuous current conduction. Variable switching frequency control is used to regulate the output voltage of the converter and pulse width modulation is used to control the dc-bus voltage. This dual control scheme is very effective to keep the dc-bus voltage nearly constant over a wide range of line and load variations. The proposed topology and control scheme have been validated by hardware results on a 250W resistive load.
This study proposes an inverter circuit topology capable of generating multilevel dodecagonal (12-sided polygon) voltage space vectors by the cascaded connection of two-level and three-level inverters. By the proper selection of DC-link voltages and resultant switching states for the inverters, voltage space vectors whose tips lie on three concentric dodecagons, are obtained. A rectifier circuit for the inverter is also proposed, which significantly improves the power factor. The topology offers advantages such as the complete elimination of the fifth and seventh harmonics in phase voltages and an extension of the linear modulation range. In this study, a simple method for the calculation of pulse width modulation timing was presented along with extensive simulation and experimental results in order to validate the proposed concept.
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