The lithography verification of critical dimension variation, pinching, and bridging becomes indispensable in synthesizing mask data for the photolithography process. In handling IC layout data, the software usually use the hierarchical information of the design to reduce execution time and to overcome peak memory usage. However, the layout data become flattened by resolution enhancement techniques, such as optical proximity correction, assist features insertion, and dummy pattern insertion. Consequently, the lithography verification software should take burden of processing the flattened data.This paper describes the hierarchy restructuring and artificial neural networks methods in developing a rapid lithography verification system. The hierarchy restructuring method is applied on layout patterns so that the lithography verification on the flattened layout data can attain the speed of hierarchical processing. Artificial neural networks are employed to replace lithography simulation. We define input parameters, which is major factors in determining patterns width, for the artificial neural network system. We also introduce a learning technique in the neural networks to achieve accuracy comparable to an existing lithography verification system. Failure detection with artificial neural networks outperforms the methods that use the convolution-based simulation. The proposed system shows 10 times better performance than a widely accepted system while it achieves the same predictability on lithography failures.
In mask fabrication, e-beam exposure equipment malfunctioning could produce erroneous masks, several consecutive mask failures in the worst case. This type of error might unexpectedly increase mask turnaround time. Due to high cost of mask fabrication and its annual growth, it is critical detecting those errors as early as possible. Since mask SEM images at after-development inspection (ADI) phase have more visible noise, edges might be hard to detect clearly using classical edge detection algorithms. In this context, we present a novel pattern error detecting algorithm to capture pattern errors in mask monitoring patterns by inspecting mask SEM images at ADI phase. The originality of this paper lies in its use of simple but powerful techniques in a series used for automated error detection. More specifically, we inspect two specific types of errors in SEM images of monitoring patterns: bridging errors in a chessboard pattern, and CD uniformity errors in a line-and-space pattern. For a chessboard pattern, we utilize both horizontal and vertical projections of image intensity histogram to find areas for inspection automatically. From one dimensional projection of the image, we identify spatial coordinates of our interests, and define a small rectangular region, called D-region. For each D-region, we determine whether a pattern bridge is likely to occur, based on the ratio of brighter pixels in it. For a line-and-space pattern, we compute base lines for CD measurement, and detect CD uniformity errors or line shift errors by applying similar one dimensional histogram analysis and CD-computation algorithm to the image. Our experimental results using real pattern images and programmed defect images support that this technique is effective and robust in detecting errors without layout data or another SEM image for comparison.
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