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We report the first measurements of in-situ flip-chip assembly mechanical stresses using a CMOS piezoresistive test chip repatterned with a fine pitch full area array. A special printed circuit board substrate was designed at Sandia and fabricated by the Hadco Corp. The flip-chip solder attach (FCA) and underfill was performed by a SEMATECH member company. The measured incremental stresses produced by the underfill are reported and discussed for several underfill materials used in this experiment.A FEM of a one-quarter section of the square assembly has been developed to compare with the measured as-assembled and underfill die surface stresses. The initial model utilized linear elastic constitutive models for the Si, solder, underfill, and PC board components. Detailed comparisons between theory and experiment are presented and discussed. IntroductionThe manufacturability and reliability of a flip-chip assembled package are strongly influenced by the mechanical stresses developed in the die-solder ball-substrate region. These stresses are produced by differential thermal contraction between substrate and die, and the stress distributidn and magnitude can be significantly changed by the presence of an underfill material. It is highly desirable to model these stresses using the Finite Element Method (FEM) stress analysis technique so that the susceptibility to mechanical failure during thermal cycling can be predicted for new geometries

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