THISdiscussion endeavors to cover the literature from October 1951 to October 1953. A few earlier items which were not covered in previous reviews are also included. Although a large number of articles have appeared in this field, many of them are concerned primarily with modifications and adaptations of the more or less standard procedures. Some of these will be found to be useful improvements.
This paper describes a new technique for identifying defects on integrated circuit. This technique detects the noise content in light emitted from defect sites. The purpose of this technique is to determine which of many light emission sites represent a defect and which represent normal devices. It reports the first phase of studies to evaluate the feasibility and potential effectiveness of this technique. The feasibility of this technique has been demonstrated by simultaneously monitoring electrical noise and the noise in the light emitted from a gallium arsenide light emission diode (LED) and a bipolar transistor. The paper will present the methodology and apparatus used to detect and analyze the noise in light emission.
Recent advances in integrated circuit technologies and in interconnect methodologies to external electronics have made it extremely difficult to conduct failure analysis from the top side of the die (1,2). Therefore analysis techniques are being developed that allow analysis from the backside of the die. The first step in this process involves gaining access to the back of the die through the packaging material. Most backside analysis techniques require that the die then be thinned and polished. This paper describes specialized equipment and procedures to meet those requirements. The equipment is relatively inexpensive compared to other approaches.
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