International audience—Hardware Trojans (HT) inserted in integrated circuits have received special attention of researchers. In this paper, we present firstly a novel HT detection technique based on path delays measurements. A delay model, which considers intra-die process variations, is established for a net. Secondly, we show how to detect HT using ElectroMagnetic (EM) measurements. We study the HT detection probability according to its size taking into account the inter-die process variations with a set of FPGA. The results show, for instance, that there is a probability greater than 95% with a false negative rate of 5% to detect a HT larger than 1.7% of the original circuit. I. Introduction The trust and security of Integrated Circuits (IC) design and fabrication is critical for sensitive fields like finance, health, and governmental communications. Due to the complexity and the high cost of IC fabrication cycle, more and more firms outsource their production. This trend gives a possibility for an adversary to introduce malicious circuit, called Hardware Trojan horse (HT), in any IC. It can either perform a Denial Of Service (DOS), deteriorate circuit performance [8], or steal sensitive information. Therefore, the HTs are considered a real threat which has gained attention from researchers. HT can be inserted at any point during the design or fabrication process from Register Transfer Level (RTL) to layout and circuit fabrication. For example in [11], authors show some techniques to insert malicious circuitry at RTL level. These HTs, which are activated with a specific pattern inputs, can leak secret key via RS232 channels. The HT, unlike a software trojan, cannot be removed once it is fabricated. So, it is better to proactively prevent the insertion of a HT: few methods have been proposed. One seminal work is known as " private circuits II " [9]. This paper describes a proof-of-concept, too costly to be implemented. A more reasonable option has been recently proposed in [5]: it uses two codes to encode the state and mix it with encoded randomness, which allows to prevent an easy triggering and has a detection capability. Otherwise it is important to detect it before it becomes effective. Previous works classify detection methods into two wide categories: destructive and non-destructive. Invasive methods destroy the chip to reconstruct successfully the GDSII an
We present the integration of the optical and electronic subsystems of a BB84-QKD fiber link. A high speed FPGA MODEM generates the random QPSK sequences for a fiber-optic delayed self-homodyne scheme using APD detectors.
IntroductionIn fiber-optic quantum key distribution (QKD) at telecommunications wavelengths, QPSK encoding of Alice's Qbits constitutes an attractive modulation format [1, 2] since it could be detected in differential interferometric schemes that need only one fiber, thus relaxing the requirements in phase and polarization stability and providing a more reliable long distance QKD link, and at the same time simplifies the system's integration and control.
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