This paper describes a method for the design and direct hardware realization of 3-level m-sequence generators. The method is based on the use of two recently introduced ternary logic primitives: the hybrid implemented U-gate and the J R K R nip-flop sequencer. Requirements for the generation of 3-level m-sequences are discussed, and the design approach is described using an example. Possible applications and extensions of the basic design and realization approach are also noted.
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