The effect of underfill material on reliability of flip chip on board (FCOB) assemblies is investigated in this study by using two-dimensional and three-dimensional finite element simulations under thermal cycling stresses from −55°C to 80°C. Accelerated testing of FCOB conducted by the authors reveals that the presence of underfill can increase the fatigue durability of solder interconnects by two orders of magnitude. Similar data has been extensively reported in the literature. It is the intent of this paper to develop a generic and fundamental predictive model that explains this trend. While empirical models have been reported by other investigators based on experimental data, the main drawback is that many of these empirical models are not truly predictive, and can not be applied to different flip chip architectures using different underfills. In the proposed model, the energy-partitioning (EP) damage model is enhanced in order to capture the underlying mechanisms so that a predictive capability can be developed. A two-dimensional finite element model is developed for stress analysis. This model accounts for underfill over regions of solder in an approximate manner by using overlay elements, and is calibrated using a three-dimensional finite element model. The model constant for the enhanced EP model is derived by fitting model predictions (combination of two-dimensional and three-dimensional model results) to experimental results for a given temperature history. The accuracy of the enhanced EP model is then verified for a different loading profile. The modeling not only reveals the influence of underfill material on solder joint durability, but also provides the acceleration factor to assess durability under life cycle environment, from accelerated test results. Experimental results are used to validate the trends predicted by the analytical model. The final goal is to define the optimum design and process parameters of the underfill material in FCOB assemblies in order to extend the fatigue endurance of the solder joints under cyclic thermal loading environments.
A generalized multi-domain Rayleigh-Ritz (MDRR) approach developed by Ling and Dasgupta (1995), is extended in this paper, to obtain the stress field in flip chip solder interconnects, under cyclic thermal loading. Elastic, Plastic and time-dependent visco-plastic analysis is demonstrated on flip chip solder interconnects. The method has been applied to other surface-mount interconnects in the past such as J-lead (Ling and Dasgupta, 1996a) and ball-grid joints (Ling and Dasgupta, 1997). The analysis results for the J-lead and ball grid joints have confirmed that the MDRR technique is capable of providing stress-strain hysteresis with adequate accuracy, at a fraction of the modeling effort required for finite element model generation and analyses. Nonlinear viscoplastic stress analysis results for flip chip interconnects without underfill are presented in this paper. The fatigue endurance of the solder joints is assessed by combining results from this stress analysis model with an energy-partitioning damage model (Dasgupta et al., 1992). The life predicted by the analytical damage model is compared with experimental results.
Flip chips are generally seen as a potential future "packaging" option providing an alternative to chip scale packages. In this work, the reliability of flip chip assemblies was analyzed using daisy chain test components on a schematic test vehicle designed to emulate a cellular phone environment printed wiring board (PWB). The flip chip components were assembled in a standard surface mount technology process, where the flip chip bumps were first dipped in a flux film. A test matrix consisting of a number of flip chip test components with different input/output configurations, PWBs, fluxes, and underfills was built up. The assemblies were tested for potential damage to the flip chips and their interconnects by thermal cycling and by mechanical shock in a drop. After testing, the root causes of the failures were analyzed. As a separate task, the stress/strain generation that occurs in the flip chips in the drop test was analyzed using simulation, in order to find the critical locations on the test PWB.
Index Terms-Ball grid array (BGA), chip scale package (CSP), direct chip attach (DCA), input/output (I/O), printed wiring board (PWB), surface mount technology (SMT).
Parametric analytical studies are conducted to investigate whether the reliability of flip-chip solder interconnects are affected by inhomogeneities in the underfill, such as settling of the filler particles. The property gradation caused by filler settling is modeled with a micromechanics formulation. The predicted property gradients are then utilized in a finite element simulation of the flip-chip assembly, to assess the impact on solder interconnect reliability.
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