The processes used for the surface planarization of the interlevel dielectrics which is one of the major problems of the multilevel interconnection CMOS technology, are becoming increasingly sophisticated. As a consequence, the reproducibility of the total process requires an accurate control of these technics in order to increase die yields. The DOPED method, developed for a non-contact on-line monitoring of flow annealing of BPSG films has been applied to the “cold” planarization techniques implemented in the CNET 0.7 µm technology. Results are obtained for TEOS deposition and etchback techniques and SOG total etchback.
CNET /CNS B.P. 98 38243 MEYLAN CEDEX FRANCE One of the very critical steps in the manufacturing process of VLSI (Very Large Scale Integrated) circuits is the reflow of PSG and BPSG (Phosphosilicate Glasses and Borophosphosilicate Glasses). The reflow consists in increasing the temperature during a given time to obtain a viscous deformation of these silica based glasses. So far, the only way 158 / SPIE Vol. 990 Chemical, Biochemical, and Environmental Applications of Fibers (1988) Downloaded From: http://proceedings.spiedigitallibrary.org/ on 06/23/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx
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