Using simulation, we examine the efficiency of several distributed, hardware-based solutions to the cache coherence problem in shared-bus multiprocessors. For each of the approaches, the associated protocol is outlined. The simulation model is described, and results from that model are presented. The magnitude of the potential performance difference between the various approaches indicates that the choice of coherence solution is very important in the design of an efficient shared-bus multiprocessor, since it may limit the number of processors in the system.

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Trace-driven simulation is commonly used to predict the performance of computer systems. However, existing tracing techniques produce traces inadequate for some studies: they do not usually record operating system references, and they produce relatively short traces. This paper explores the impact of these trace distortions on the performance estimates of unaprocessor memory hierarchies using multiprogramming workloads. We used a hardware monitor to capture traces under a variety of workloads and operating systems. Our monitor captures every reference and can record arbitrarily long traces. We quantify memory hierarchy performance using traces of the SPEC SDMl.1 benchmark suite executing on an a486 CPU. To evaluate variations due t o operating systems, we compare these results under both Mach 3.0 and UNIX Sys V R4. We conclude that for current uniprocessors, long but incomplete traces result in modest errors in estimated performance, but for proposed architectures with large delays to main memory, the errors can be significant.