Electronic-dispersion compensation (EDC) techniques are being explored in OC-192 metro and long-haul links to combat dispersion/intersymbol interference (chromatic and polarization mode), noise (optical and electrical), and non-linearities (fiber, photodiode, laser). In this paper, a 9.953 to 12.5Gb/s MLSE receiver, as shown in Fig. 13.2.1, is presented. The receiver is implemented via an AFE IC and a digital equalizer IC that are packaged in a 23×17mm 2 261-pin MCM. The AFE IC is implemented in a 0.18µm 3.3V GHz SiGe BiCMOS process. The digital IC implements the MLSE algorithm and is fabricated in a 0.13µm 1.2V CMOS process.The architecture of the AFE IC is shown in Fig. 13.2.2. It features a VGA, a 4b flash ADC, a dispersion-tolerant clock-recovery unit (CRU), and a 1:8 DEMUX. The ac-coupled line-rate input (9.953 to 12.5Gb/s) can be single-ended or differential. The input signal is amplified by the VGA and then sampled by the ADC. The CRU recovers a line-rate clock for the ADC and the DEMUX. The 4b line-rate ADC samples are demultiplexed 1:8 to generate a 32b LVDS interface to the digital chip (see Fig. 13.2.1).The 3-stage VGA in Fig. 13.2.2 incorporates an analog MUX to achieve a 40dB tunable gain range and an enhanced linearity to meet the requirements of both amplified and un-amplified links. The gain sensitivity to process variations is reduced by employing a replica bias circuit (not shown) to generate source voltage V1 for M1, which is input to the gain-control block, as shown in Fig. 13.2.3. A gain-insensitive offset control maintains a constant offset independent of the input power. Offset control balances the noise variance of '1's and '0's in OSNR-limited links. The need for both single-ended and differential inputs combined with the need for input offset adjustment result in the input-termination scheme in Fig. 13.2.2. A 50Ω input termination is achieved with an S 11 < -15dB up to 7.5GHz and S 11 < -10dB up to 20GHz.The ADC architecture, shown in Fig. 13.2.2, has one stage of preamplifiers followed by two stages of metastability FFs (ADC FFs) and a Gray encoder. The Gray encoder limits coding errors to 1 LSB, minimizing their impact on the BER. The ADC can be configured between a 4b and a power-saving 3b mode. The cascode pre-amp reduces VGA output loading. Isolation between the preamps, the ADC back-end (ADC FFs and the encoder), and the DEMUX is critical. Guard rings are placed between the pre-amps and the ADC back-end, and between the ADC back-end and the DEMUX. The ground and substrate connections of the pre-amps and the ADC FFs are shared to minimize ground bounce. The DEMUX has its own supply, but it shares the same bias current as the ADC FFs. The swing in the digital blocks is made programmable to strike a balance between substrate injection and noise immunity.The CRU shown in Fig. 13.2.2 is a bang-bang PLL [1] with a fast differentially tuned VCO and phase filtering that enables clock extraction in the presence of a closed eye. Fiber non-linearities and dispersion spreads the zero crossings...
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