This paper introduces the concept of delay regulation as a means of controlling circuit delay variations from chip to chip, which is especially important in VLSI products. An embodiment of this concept which applies a phase-locked loop to individually control chip performance and power is presented together with computer-simulated results of an example design. It is shown that accurate delay equations and the potential for improved product yield result from application of the concept. The circuit overhead for large circuits is shown to be negligible. Application to a wide range of logic circuit types is also described. IntroductionContinuing improvements in both lithography and the control of process steps in the manufacture of integrated circuits have resulted in shortened logic and array circuit delays and reduced power dissipation. However, manufacturing variability dilutes these improvements by causing designers to specify a machine based on the longest delays and the hottest (fastest) chips. Many factors contribute to this variability: process steps, such as mask alignment and silicon doping, power supply voltage, power distribution, and operating temperature [1]. These factors afifect the characteristics of the devices in the circuits or their operating conditions and are included in a delay equation (an analytic expression for logic gate delay), and thus variations in these factors result in a distribution of delay values. The equation typically yields a tolerance on the computed delay values of ±50%. Reference [2] gives an example of a system which has tolerances of this magnitude. The designer is thus required to partition the critical circuit path (a serial connection of circuits which has a delay that determines the machine's maximum operating speed) on multiple chips to maximize the statistical advantage of manufacturing differences; this partitioning statistically minimizes the overall path
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