Water was diffused into very dry thermal SiO2 films under conditions such that the penetration of water related electron trapping centers was of the order of the oxide thickness. In both dry oxides and water diffused oxides, production of negative bulk oxide charge Qot and positive interface charge Qit by an avalanche-injected electron flux was observed. The efficiencies of both processes were enhanced by water indiffusion. Analysis of the kinetics of charge generation indicated that production of trapped electron centers (Qot ) was required for subsequent production of interface states and charge (Qit ). Models for both processes are discussed. We suggest that inelastic collisions of conduction electrons with the trapped electron centers releases mobile hydrogen atoms or excitons. The mobile species migrate to the Si–SiO2 interface and form states and fixed charge.

Two experimental observations are reported concerning the degradation of the Si–SiO2 interface during electron injection in metal-oxide-semiconductor structures. First, the generation of the interfacial positive charge during avalanche injection can be strongly inhibited by employing magnesium, instead of aluminum, as gate metal, or enhanced by employing gold. This correlates with the different work functions of the metals. Second, during negative bias high-field injection in Al-gate capacitors with thin oxides (≲100 Å), a threshold in gate voltage, of 7–8 V, is found for the generation of the positive charge. Both observations are consistent with a model which assumes that holes generated in the anode by hot electrons, via emission of surface plasmons, are injected into the SiO2 and are subsequently trapped at the Si–SiO2 interface. Other possible mechanisms are also discussed.

Early stages in thin film metal-silicon and metal-SiO2 reactions under rapid thermal annealing conditions: The rapid thermal annealing/transmission electron microscopy technique

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Electron trapping in silicon dioxide is reduced by nitrogen annealing in a furnace system with very low moisture content and special cooling techniques. The flatband voltage shift resulting from injected hot electrons is significantly reduced by the annealing together with the interface states generated. The trapped charge is laterally nonuniform when the oxide is not annealed. From photo I-V measurement, the density of electrons trapped in the bulk of the oxide is reduced by this treatment. The distribution of the trapped charge changes from a uniform distribution in the bulk for a 1-h anneal to a distorted U shape distribution, with a larger build-up on the aluminum-silicon dioxide side for a 17-h anneal. The density of trapped charge close to the silicon-silicon dioxide interface is reduced and thus the smaller flatband voltage shift. With the reduction in bulk change, interface state charge beomes important.

Impurities initially present on a Si surface can be detected using the photo I-V technique. An Al impurity deposited to a thickness less than 8 Å on a silicon substrate which was subsequently oxidized, capped by a chemically vapor deposited (CVD) SiO2 layer, and incorporated into a capacitor structure with an Al gate electrode was found mostly near the interface between the thermal and CVD oxides using the photo I-V technique. This impurity layer which was probably converted to Al2O3 showed greatly enhanced electron trapping compared to either oxide layer.