A novel circuit architecture and algorithm is preThere is some evidence that methods which involve resented for the efficient implementation of a matrix inversion currence, such as Sherman-Morrison, iterative methods, and unit. The division-free algorithm yields a scaled version of the v. l' S.'iE inverse and the scaling factor. Based on the Sherman-Morrison variou formsfiven rotatns-asd inversion typically formula, the proposed architecture is characterized by regular, provlde better numerical robustness and precision than convenlocally-connected arrays of processing units and simple iterative tional direct inversion methods [6]. Simulations have shown processing. It is especially well-suited for covariance matrices, that this is true for the proposed method. Furthermore, a or any other matrix which can be constructed from rank-one means of dynamic scaling control was devised to maximize updates of an initial matrix whose inverse is known. While it the precision of the result when integer arithmetic is used.constitutes an ideal solution for antenna array MMSE (minimum mean-square error) processing, it can also be generalized to many II. OPTIMAL COMBINING USING MINIMUM MEAN other applications with little effort. Implementation results of a SQUARE ERROR CRITERIA heavily pipelined matrix inverter on a Xilinx Virtex-I FPGA are presented, including cost in logic slices and maximum clock Figure 1 shows a typical M x M Multi-Input Multi-Output frequency. The cost / complexity of the proposed solution is com-(MIMO) system. In a Layered Space-Time (LST) scheme [10], parable to, and in many cases better than, known alternatives, each transmitting antenna's signal is at some point estimated by passing through a linear weight-and-sum structure (spatial filter), where the optimal weight vector can be chosen accordIing to the zero-forcing (ZF) or the minimum mean-square error Matrix inversion is a common operation in many signal (MMSE) criterion. processing problems, including most block adaptation methods > used in adaptive communication systems. In previous efforts [1], [2], implementation in hardware is often non-trivial because of the need for complex operators, * : e.g. division or square root. Many proposed architectures rely Tx Rx on some form of factorization such as Cholesky [3] or QR [4], [5], [6]. The latter class is of particular interest, and
This paper presents a practical implementation of a Layered Space-Time (LST) receiver targeting a Xilinx Virtex-II FPGA. The architecture is based on multipass burst processing, and includes burst buffers for each antenna, channel parameter estimation modules exploiting a training sequence, and a simple matrix inversion adaptation mechanism. LST architectures involve significant implementation complexity and various refinements have been proposed in the literature to mitigate this aspect. Our receiver is based on novel modifications to the standard LST algorithm which enable unprecedented implementation simplicity, avoiding complex operations such as divisions and square roots, while suffering a negligible BER degradation.
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