Hierarchical Temporal Memory (HTM) is an online machine learning algorithm that emulates the neo-cortex. The development of a scalable on-chip HTM architecture is an open research area. The two core substructures of HTM are spatial pooler and temporal memory. In this work, we propose a new Spatial Pooler circuit design with parallel memristive crossbar arrays for the 2D columns. The proposed design was validated on two different benchmark datasets, face recognition, and speech recognition. The circuits are simulated and analyzed using a practical memristor device model and 0.18 μm IBM CMOS technology model. The databases AR, YALE, ORL, and UFI, are used to test the performance of the design in face recognition. TIMIT dataset is used for the speech recognition.
The fourth industrial revolution is destroying traditional business models of companies. In order to maintain the current level of competitiveness, companies must adapt to changing conditions, draw up and implement strategies for introducing digital technologies into their business processes. The article presents a structured approach for systematic modeling of business digitalization.
Abstract-Simple current mirrors with semiconductor resistive loads suffer from large on-chip area, leakage currents and thermal effects. In this paper, we report the feasibility of using memristive loads as a replacement of semiconductor resistors in simplistic current mirror configuration. We report power, area and total harmonic distribution, and report the corner conditions on resistance tolerances.
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