Graphene p-n junctions could be the building blocks of future nanoelectronic circuits. While the conductance modulation of graphene p-n junctions formed in devices with one bottom and one top gate have received much attention, there is comparatively little work done on devices with two top gates. Here, we employ tight-bind Hamiltonians and non-equilibrium Green function method to compute in a systematic way the dependence of the conductance of graphene p-n junctions, formed in a device with two top gates, on the device parameters. We present our results in a compact and systematic way, so that the effect of each parameter is clearly shown. Our results show that the device conductance can be effectively modulated, and that graphene devices with two top gates may be used as basic elements in future carbon-based nanoelectronic circuits.
This paper showcases the design and development of a DC-DC converter with one input and four outputs using a high frequency resonant air-core transformer. The transmitter to receivers air-gap is 25 mm. Practical tuning equations were derived for multiple receivers which allow the converter to be optimised for overall efficiency and unity power factor at the transmit coil (i.e. zero reflected reactance). Experiments were conducted using two receive coil structures, one with four equally shaped adjacent coils in a single PCB, and the other with four differently-shaped coils featuring overlapping traces to maximise the coupling factor with the transmitter and minimise the coupling factor between the receivers. The two structures were tested and compared using the same transmitter, driven by a single-ended 13.56 MHz Class EF inverter. Single-ended Class D rectifiers were implemented at the receive side. Experiments were performed, first with equal AC test loads, and afterwards with the addition of the rectifiers and buck converters to regulate each of the four output voltages to 15 V independently. The results of the experiments implementing adjacent coils demonstrate that equal distribution of power can be achieved by modifying the tuning capacitances at the receivers with the AC loads; however, when the voltage-regulating buck converters were introduced at each output, it was only with the coil structure with overlapping traces that the required power of 10 W at each output was achieved.1 matrices and vectors are marked as bold.
Class EF inverters have been widely used recently as primary coil drivers for wireless power transfer applications since they achieve constant output current across a range of link coupling factor values. As the operating frequency that the inductive link is tuned at increases the traditional circuit design techniques that are based on first order calculations fail to represent the inverter behaviour accurately. In this paper, we present a novel method of modelling Class EF inverters that is based on state space representation of the circuit and thus providing the highest accuracy possible. Our method consists of a combination of analytical and numerical calculations in such manner that any parasitic component of the circuit, such as the nonlinear output capacitance of a power switch, can be included in the tuning process.
The additional complexity of Class EF and Class Φ inverters compared with their Class E counterparts, combined with parasitic effects becoming more prevalent as frequency and power levels increase, results in poor accuracy from traditional design methods, and usually additional iterations of manual retuning are required. Furthermore, after making these additional iterations, it is practically impossible to ensure that all the desired design conditions are met in hardware, due to the number of degrees of freedom in these circuits. In this work, we propose an approach to simulating and tuning Class EF/Φ inverters, with various levels of accuracy depending on the level of knowledge of the system parasitics. Our method is composed of a combination of analytic and numerical solving methods, thus providing both insight on the progression of the algorithm and computational robustness. The aim of our algorithm formulation is to enable solutions to be found in an automated and fast way. The novelty in our work lies in the design method's concurrent capability to provide a generalized set of design inputs (e.g., dc to ac current gain, arbitrary drain voltage slope at turn ON, Φ-branch resonance, etc.), inclusion of board and device nonlinear parasitics, and the ability to design within the set of preferred component values. An example is shown for the design of a 50-W, 13.56-MHz inverter where the experimental setup approaches the theoretical efficiency of 97%, whilst maintaining all of the other design requirements. The algorithm changes the
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