In this paper we present a measurement-based worst-case execution time (WCET) analysis method. Exhaustive end-to-end execution-time measurements are computationally intractable in most cases. Therefore, we propose to measure execution times of subparts of the application code and then compose these times into it safe WCET bound. This raises a number of challenges to be solved. First. there is the question of how to define and Subsequently calculate adequate subparts. Second, a huge amount of test data is required enforcing the execution of selected paths to perform the desired runtime measurements. The presented method provides solutions to both problems. In a number of experiments we show the usefulness of the theoretical concepts and the practical feasibility by using current state-of-the-art industrial case studies from project partners

In this paper we present a new measurement-based worst-case execution time (WCET) analysis method. Exhaustive end-to-end measurements are computationally intractable in most cases. Therefore, we propose to measure execution times of subparts of the application. We use heuristic methods and model checking to generate test data, forcing the execution of selected paths to perform runtime measurements. The measured times are used to calculate the WCET in a final computation step. As we operate on source code level our approach is platform independent except for the run time measurements performed on the target host.We show the feasibility of the required steps and explain our approach by means of a case study.

The counter-intuitive timing behavior of certain features in superscalar processors that cause severe problems for existing worst-case execution time analysis (WCET) methods is called timing anomalies.In this paper, we identify structural sources potentially causing timing anomalies in superscalar pipelines. We provide examples for cases where timing anomalies can arise in much simpler hardware architectures than commonly supposed (i.e., even in hardware containing only in-order functional units). We elaborate the general principle behind timing anomalies and propose a general criterion (resource allocation criterion) that provides a necessary (but not sufficient) condition for the occurrence of timing anomalies in a processor.This principle allows to state the absence of timing anomalies for a specific combination of hardware and software and thus forms a solid theoretic foundation for the time-predictable execution of real-time software on complex processor hardware.

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-This paper presents a scalable approach to interface between a time-triggered distributed hardware-in-theloop (HIL) simulator and the system under test (SUT) via Smart Virtual Transducers (SVTs). An SVT is an element of an HIL simulator and implements two interfaces -a standardized digital interface to a time-triggered transducer network and a transducer-specific interface. The main contribution of the approach is a separation of the execution of the simulation model and the deterministic interaction via an arbitrary transducer interface. The benefit of such separation is the temporal decoupling between simulation model execution and interaction with the SUT. Furthermore, the approach leads to a reduction of complexity of the simulation setup. The application of the approach is shown by an SVT prototype that is used to simulate a temperature sensor.