The experimental and modeling study of bias-stress-induced threshold voltage instabilities in amorphous indium-gallium-zinc oxide thin film transistors is reported. Positive stress results in a positive shift in the threshold voltage, while the transfer curve hardly moves when negative stress is induced. The time evolution of threshold voltage is described by the stretched-exponential equation, and the shift is attributed to the electron injection from the channel into interface/dielectric traps. The stress amplitudes and stress temperatures are considered as important factors in threshold voltage instabilities, and the stretched-exponential equation is well fitted in various bias temperature stress conditions.

We have investigated the static and dynamic bias stress-induced charge trapping and detrapping phenomenon in amorphous indium-gallium-zinc oxide thin film transistors. It is observed that the charges trapped after electron injection in the interface and bulk traps are unstable and slowly decay over time. The stretched-exponential equation, which can be derived based on the trapping/detrapping of charges to/from existing traps and continuous redistribution of charges in bulk dielectrics, is successfully applied in fitting the time dependence of the threshold voltage shift during the stress and recovery phases under dynamic stresses. The characteristic time constants decrease with increasing temperature and drain bias during the recovery phase. Under dynamic stresses with various frequencies, the threshold voltage shift strongly depends on the frequency of dynamic stresses, i.e., a high frequency stress results in a small threshold voltage shift and a long lifetime. The stress-induced threshold shift phenomenon is observed to be relieved after a long-time low temperature post thermal annealing process and device passivation with an aluminum oxide layer.

A comparative study was made of the performance and electrical instabilities in amorphous indium-gallium-zinc oxide (a-IGZO) thin film transistors with Al2O3 and Al2O3/SiNx gate dielectrics. Steeper subthreshold slope is observed in Al2O3 devices, which shows that the density of trap states at the interface of a-IGZO/Al2O3 is lower than that of a-IGZO/SiNx. Under high bias-stresses, a larger degradation is observed in Al2O3/SiNx devices. The device degradation for both devices are mainly attributed to the charge trapping phenomenon, but the different time dependence of threshold voltage shift shows that trapped electrons are more easily redistributed inside the Al2O3 dielectrics.

We investigate the effects of ambient atmosphere on the electrical performance of p-type tin monoxide (SnO) thinfilm transistors (TFTs), and present the effective method for the passivation of SnO TFTs using a SU-8 organic layer. The experimental data shows that the SnO TFTs without a passivation layer suffer from the electrical performance degradation under humid environments, which implies that the formation of the passivation layer is necessary in p-type SnO TFTs for the stable operation of the devices. The SU-8 organic layer was successfully incorporated as a passivation layer of SnO TFTs. The SnO TFTs with a SU-8 passivation layer exhibit very similar transfer characteristics with those without a passivation layer, and show much improved long-term durability and bias stress stability compared with the SnO TFTs without a passivation layer under air environments.Index Terms-P-type SnO TFTs, SU-8 passivation layer, humidity, long-term durability, bias stress stability.

We demonstrated highly stable multilayer molybdenum disulfide (MoS2) field-effect transistors (FETs) with negligible hysteresis gap (ΔV(HYS) ∼ 0.15 V) via a multiple annealing scheme, followed by systematic investigation for long-term air stability with time (∼50 days) of MoS2 FETs with (or without) CYTOP encapsulation. The extracted lifetime of the device with CYTOP passivation in air was dramatically improved from 7 to 377 days, and even for the short-term bias stability, the experimental threshold voltage shift, outstandingly well-matched with the stretched exponential function, indicates that the device without passivation has approximately 25% larger the barrier distribution (ΔE(B) = k(B)T(o)) than that of a device with passivation. This work suggests that CYTOP encapsulation can be an efficient method to isolate external gas (O2 and H2O) effects on the electrical performance of FETs, especially with low-dimensional active materials like MoS2.

We have investigated the effects of vacuum annealing on the optical and electrical properties of the p-type copper-oxide thin-film transistors (TFTs). The vacuum annealing of the copper-oxide thin-film was performed using the RF magnetron sputter at various temperatures. From the x-ray diffraction and UV-vis spectroscopy, it is demonstrated that the high-temperature vacuum annealing reduces the copper-oxide phase from CuO to Cu 2 O, and increases the optical transmittance in the visible part of the spectrum. The fabricated copper-oxide TFT does not exhibit the switching behavior under low-temperature vacuum annealing conditions. However, as the annealing temperature increases, the drain current begins to be modulated by a gate voltage, and the TFT exhibits a high current on-off ratio over 10 4 as the vacuum annealing temperature increases over 450 • C. These results show that the vacuum annealing process can be an effective method of simultaneously improving the optical and electrical performances in p-type copper-oxide TFTs.

We have investigated the effects of air-annealing on the electrical performance of the p-type tin oxide thin-film transistors (TFTs). The air-annealing of the tin oxide thin-film was made using a mini furnace at various temperatures. From the x-ray photoelectron spectroscopy (XPS) and x-ray diffraction (XRD) data, it is demonstrated that the phase of tin oxide partially transforms from SnO to SnO 2 with an air-annealing process, and it accelerates as the annealing temperature increases. The electrical performance of the p-type tin oxide TFT with a channel thickness of 25 nm exhibits much improved electrical performance when air-annealed at 230 • C for 1 h, but a decrease of the on-current is observed with an ambipolar operation in 260 and 290 • C air-annealed devices. Based on the XPS, XRD, and Hall measurement data, the reduced hole concentration inside the channel due to the recombination with electrons from SnO 2 is believed to be the reason for the electrical performance improvement in 230 • C air-annealed p-type tin oxide TFTs, and a partial formation of n-type SnO 2 channel is considered as the plausible reason for the ambipolar operation in tin oxide TFTs with high annealing temperatures. Our experimental results show that there is an optimum air-annealing temperature which can improve the electrical performance in p-type tin oxide TFTs.

We investigate the charge transport mechanism and subgap density of states (DOS) in p-type Cu2O thin-film transistors (TFTs) using the bias and temperature dependence of the drain currents. Among several charge transport mechanisms, the experimental data are well matched with a multiple trapping and release model, which suggests that the charge transport in the Cu2O TFT is mainly limited by trap states at grain boundaries or dielectric/semiconductor interface. The subgap DOS is extracted based on the Meyer-Neldel rule. Large density of subgap states is extracted, which is considered to be the reason of low mobility in fabricated Cu2O TFTs.