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This paper describes a new mixed-signal VLSI implementation of neural networks for low power and asynchronous operation. The linearised transconductance produces the synaptic function of multiplication, weight programming, and summation of synaptic currents for the neuron. The synapse circuit is designed with 8 transistors, by compensating the non-linearity of MOSFET resistance in the triode region.The flexible configuration of synapse accommodates either the pulse-based implementation or any analogue synapse with multiplication or summation. The operation speed of individual synapse is up to 300 Mega operations with the power consumption of less than 33µW, from the chip design using 0.18µm(3.3V) CMOS process. The accuracy is extendable in modular structure, though the current design is based on 8-bit accuracy. The overall power consumption can be less in practice, as individual synapse only demands the power when there is an active signal.The advantages of proposed VLSI implementation are the large scale implementation with low power consumption and its adaptable features to various requirements from different paradigm of neural network architecture, depending on the demand of asynchronous architecture, pulse/spike-based architecture, or the accuracy requirements.

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