SiGe quantum dot single-hole transistor fabricated by atomic force microscope nanolithography and silicon epitaxial-regrowth Ge/Si quantum-dot metal-oxide-semiconductor field-effect transistor
Polycrystalline silicon (poly-Si) thin-film transistors (TFTs) incorporating germanium (Ge) quantum dots (QDs) in the gate oxide were fabricated as efficient blue to near ultraviolet phototransistors for light detection and amplification. Under 405–450 nm light illumination, Ge QDs poly-Si TFTs exhibit not only strong photoresponses in the drive current but also much improved subthreshold characteristics than that measured in darkness. This originates from the fact that only photoexcited holes within Ge QDs are injected into the active channel via vertical electric field and contribute excess mobile carriers for photocurrent but without the associated photogenerated electron induced junction barrier lowering.
A Coulomb blockade (CB) thermometer has been experimentally demonstrated based on the temperature dependence of a Ge quantum-dot (QD) single-hole transistor (SHT). The Ge-QD SHT features distinctive current peaks/plateaus, sharp differential conductance (GD) dips up to temperature 120K. The full-width-at-half minimum, V1/2, of the GD dips directly scale with temperature following the material parameterindependent equation of eV1/2 ~ 5.44kBT, providing the primary thermometric quantity. Also the depths of the GD dips increases with 1/kBT as expected from CB theory of ΔGD/GD0 = EC/6kBT. This experimental demonstration indicates that our Ge-QD SHT offers an effective building block for ultrasensitive CB primary thermometers with the detection temperature as high as 115K.
We have developed a simple, manageable, and selforganized manner ⎯ thermally oxidizing SiGe nanocavity for precisely controlling Ge quantum dot (QD) number, position, and tunnel path, which is crucial for effective single-electron tunneling devices. The internal structure properties of Ge QDs were systematically characterized. The effectiveness of Ge QD placement is evidenced by high performance Ge QD single electron transistors (SETs), featuring with clear Coulomb staircase and Coulomb-blockade oscillation behaviors at room temperature.The newly emerging field of zero-dimensional quantum dots (QDs), enabled by materials nanoscience and nanotechnology, has opened the door for offering entirely new possibilities for improving the efficiency and expanding the functionality of electronics, photonics, and even photovoltaic devices. Singleelectron transistors (SETs), consisting of a single QD weakly coupled to adjacent electrodes via thin tunnel barriers, are an ultimate electronic device for controlling current with a single charge precision based on the so-called Coulomb blockade effect. In the past two decades, functional SETs have been extensively demonstrated either at the expense of complex and formidable fabrication techniques, or based on some fortuitous phenomena. Leaping over the proof-of-principle level, we are approaching the stage of realizing optimal designed QD structures for practical applications, using cost-effective Si techniques. Deep understanding and characterization of chemical, structural, strain, shape, and interfacial properties of QDs are essential, since this kind of information gives all the important parameters for tailoring electronic and optical properties of QDs. To better control electron tunneling and coupling in SETs, it is also essential to control the tunnel paths and make nanoscopic electrical contacts with specific nanoscale features.We have demonstrated a manageable growth of designed Ge QD structures in a self-organized manner ⎯ thermal oxidation of SiGe nanocavities [1, 2]. We enabled to place a single Ge QD in the center of an oxidized SiGe nanocavity, which is separated from electrodes by SiO 2 or Si 3 N 4 spacers. The tunnel paths between electrodes and QDs are directly determined by the deposited spacer thickness. This result strongly motivates us to fabricate effective single electron transistors (SETs) with controllable QD number and position and in turn currentvoltage characteristics.In this paper, the fabrication of Ge QD SETs began with a 100 nm-thick SiO 2 deposition on top of a (100) p-Si substrate. After a 70 nm-thick polycrystalline Si (poly-Si) layer deposition, a cavity in 50 × 50 nm 2 were defined using electron-beam lithography (EBL) and plasma etching. The cavity were further shrank to 20 × 20 nm 2 by depositing 15 nm Si 3 N 4 spacer. Next, a 50 nm-thick poly-Si 0.9 Ge 0.1 was deposited to refill the cavity and then directly etched back to leave a 20 nm-thick poly-SiGe at the cavity bottom, ready for subsequent oxidation in H 2 /O 2 ambient at 900 o C. The k...
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