A signal detection system using noise statistical processing is proposed. By approaching the problems of low voltage and high noise from miniaturization of a device from a stochastic point of view, a faint-signal receiving system that can effectively detect subthreshold and noise level signals has been developed. In addition, an alternative to statistical processing is proposed, and would be successfully implemented on a circuit. For the proposed signal detection method, the detection sensitivity was investigated using numerical simulation, and the detection sensitivity was sufficiently high to detect even a signal with a signal-to-inherent-noise ratio of −14 dB. Thus, it is anticipated that the application of this system to an integrated circuit will have a significant impact on signal processing.

Abstract:A stochastic signal detection circuit that uses a nonlinearity reduction technique is designed using a 65-nm CMOS process. The fabricated chip demonstrates the feasibility of stochastic signal detection at 500 MS/s. Keywords: signal detection, comparator, mismatch, CMOS Classification: Integrated circuits I, vol. 57, no. 11, pp. 2825I, vol. 57, no. 11, pp. -2833I, vol. 57, no. 11, pp. , Nov. 2010 J. Lin and B. Haroun, "An embedded 0.8 V/480 μW 6b/2 MHz flash ADC in 0.13-μm digital CMOS process using a nonlinear double interpolation technique," IEEE J. References

This paper introduces several techniques for achieving RF and analog CMOS circuits for wireless communication systems under ultra-low-voltage supply, such as 0.5 V. Forward body biasing and inverterbased circuit techniques were applied in the design of a feedforward Δ-Σ A/D modulator operating with a 0.5 V supply. Transformer utilization is also presented as an inductor area reduction technique. In addition, application of stochastic resonance to A/D conversion is discussed as a future technology.

A stochastic flash analog-to-digital converter (SF-ADC) utilizing device mismatch is designed using a 65-nm CMOS process. Since the proposed SF-ADC uses thresholds determined by the input-referred comparator offsets, large input-referred offsets are allowed. The quantization error and nonlinearity of SF-ADC are demonstrated, and the input range is enlarged by using nonlinearity reduction technique. At 1.6 GS/s sampling, the designed ADC achieves 34.7-dB SFDR and 29.0-dB SNDR without any calibration circuits despite the large input-referred offset of 102 mV. At this conversion speed, it consumes 134 mW with a 1.2-V power supply.

No abstract

No abstract

No abstract