Thermal oxidation and chemical vapor deposition (CVD) are two major methods to form silicon oxide films. Many researchers 1-10 have studied to characterize and understand the bulk silicon oxide and the SiO 2 /Si interface. Low-temperature deposition of SiO 2 (<500ЊC) is possible with CVD, which has been used for intermetal dielectric (IMD) and interlayer dielectric (ILD). 11-13 Low-temperature deposition is also required in the thin-film-transistor liquid crystal display (TFT-LCD) process to enable utilization of low-cost glass substrates. So far, hydrogenated amorphous silicon (a-Si:H) TFTs with silicon nitride as a gate insulator have been used for LCDs, because a-Si for active layers can be easily deposited on large-area, inexpensive glass substrates at temperatures below 350ЊC. 14 On the other hand, the electron mobility in polysilicon is higher than in a-Si, and one of the advantages of poly-Si TFTs is their potential for integrated-array driver circuits, which can significantly reduce the number of interconnections from the pixel TFT to the peripheral circuit. The development of a low-temperature process for the deposition of poly-Si and gate insulator is required. In this case, silicon oxide is preferred as a gate insulator, since poly-Si has been known to have good interface properties with silicon oxide. 15 So far, in silicon oxide CVD processes, a silane (SiH 4 ) chemistry, for example, SiH 4 /N 2 O or SiH 4 /O 2 , has been used. 16 The study for the interface characterization has been focused on the silane chemistry CVD process. 17-20 Silicon oxide by tetraethylorthosilicate (TEOS) chemistry is believed to be a candidate for the gate oxide, together with that by silane chemistry. Although the TEOS molecule has ethoxy groups (OC 2 H 5 ), it has been known that carbon impurities are not a problem. TEOS processes have been widely studied with various methods such as plasma-enhanced chemical vapor deposition (PECVD), electron cyclotron resonance (ECR) plasma CVD, and ozone-based CVD. 21-24 Silicon oxide films by TEOS/O 3 CVD processes have especially been studied by many researchers and have mainly been used for IMD and ILD due to their good step coverage. However, the interface characterization for gate oxides has rarely been studied yet.In this study, electrical properties of the bulk silicon oxide and the SiO 2 /Si interface by TEOS/O 3 CVD was investigated using current-voltage (I-V) and capacitance-voltage (C-V) measurements. Using the Terman method, interface properties such as interface trap density distribution (D it ) were studied as functions of process parameters such as deposition temperature and TEOS/O 3 ratio. ExperimentalTEOS (99.999%) vapor was supplied to the reactor by flowing nitrogen (99.999%) through a TEOS bubbler which was heated at 65ЊC. N 2 dilute gas was used to maintain the total gas flow rate constant in the reactor. Ozone flow rate was controlled by the ozone generator power with constant O 2 (99.999%) gas flow rate. TEOS carried by N 2 gas was mixed with ozone immediately prio...