In this paper, the leakage-based variant of the Least Mean Mixed Norm (LMMN) algorithm, the leaky Least Mean Mixed Norm (LLMMN) algorithm, is derived. The proposed algorithm will help mitigate the weight drift problem expe-rienced in the conventional Least Mean Square (LMS) and Least Mean Fourth (LMF) algorithms. The aim of this paper is to derive the LLMMN adaptive algorithm and perform the transient analysis using the energy conservation relation framework. Finally, simulation results are carried out to support the theoretical findings, and show improved performance obtained through the use of LLMMN over the conventional LMMN algorithm in a weight drift environment. Index Terms-Adaptive filters, weight drift, leaky least mean mixed norm.
In this paper we investigate the blocktype pilot channel estimation for orthogonal frequency division multiplexing (OFDM) systems. The estimation is based on the minimum mean square error (MMSE) estimator and the least square (LS) estimator. We derive the MMSE and LS estimators' architecture and investigate their performances. We prove that the MMSE estimator performance is better but computational complexity is high, contrary the LS estimator has low complexity but poor performance. For reducing complexity we proposed two different solutions which are the Simplified Least Square (SLS) estimator and the modified MMSE estimator. In the SLS estimator, we apply an auto-correlation function with the LS estimator to remove the noise. In the modified MMSE estimator, we consider only the significant energy samples and ignore the remaining noisy samples. Based on this idea we introduce the modified MMSE estimator. We evaluate estimator's performance on basis of mean square error and symbol error rate for 16 QAM systems using MATLAB.
Mixed-signal processing systems especially data converters can be reliably tested at high frequencies using on-chip testing schemes based on memory. In this thesis, an on-chip testing strategy based on shift registers/memory (2 k bits) has been proposed for digital-to-analog converters (DACs) operating at 5 GHz. The proposed design uses word length of 8 bits in order to test DAC at high speed of 5 GHz. The proposed testing strategy has been designed in standard 90 nm CMOS technology with additional requirement of 1-V supply. This design has been implemented using Cadence IC design environment.The additional advantage of the proposed testing strategy is that it requires lower number of I/O pins and avoids the large number of high speed I/O pads. It therefore also solves the problem of the bandwidth limitation that is associated with I/O transmission paths. The design of the on-chip tester based on memory contains no analog block and is implemented entirely in digital domain. In the proposed design, low frequency of 1 MHz has been used outside the chip to load the data into the memory during the write mode. During the read mode, the frequency of 600 MHz is used to read the data from the memory. A multiplexing system is used to reuse the stored data during read mode to test the intended functionality and performance.In order to convert the parallel data into serial data at high frequency at the memory output, serial converter has been used. By using the frequencies of 1.25 GHz and 2.5 GHz, the serial converter speeds up the data from the lower frequency of 600 MHz to the highest frequency of 5 GHz in order to test DAC at 5 GHz.
The aim of this paper is to develop a high resolution image from a sequence of low resolution compressed images. An image with improved resolution is desired in almost all of the applications to enhance qualitative features and is reported to be achieved by Super Resolution Image Reconstruction (SRIR). Some low resolution images of same scene which are usually rotated, translated and blurred are taken to form a super resolution image. The image registration operation orients translated, scaled and rotated images in similar way to that of source image. Lifting Wavelet Transform (LWT) with Daubechies4 coefficients is applied to color components of each image due to its less memory allocation compared to other techniques. Further Set Portioning in Hierarchical Trees (SPIHT) algorithm is applied for image compression as it possess lossless compression, fast encoding/decoding, adaptive nature. The three low resolution images are fused by spatial image fusion method. The noise component is removed by dual tree Discrete Wavelet Transform (DWT) and blur is removed by blind de-convolution or iterative blind de-convolution. Finally, the samples are interpolated to twice the number of original samples to obtain a super resolution image. The structural similarity for each intermediate image compared to source image is estimated via objective analysis and high structural similarity is observed for image constructed by the proposed method.
In this paper an event-driven (ED) digital signal processing system (DSP), Analog-to-digital converter(ADC) and Digital-to-analog converter(DAC) operating in continuous-time (CT) with smart dust as the target application is presented. The benefits of the CT system compared to its conventional counterpart are lower in-band quantization noise and no requirement of a clock generator and anti-aliasing filter, which makes it suitable for processing burst-type data signals. A clock less EDADC system based on a CT delta modulation (DM) technique is used. The ADC output is digital data, continuous in time, known as "data token". The ADC used an un buffered, area efficient, segmented resistor string (R-string) feedback DAC. This DAC in component reduction with prior art shown nearly 87.5% reduction of resistors and switches in the DAC and the D flip-flops in the bidirectional shift registers for an 8-bit ADC, utilizing the proposed segmented DAC architecture. The obtained Signal to noise distortion ratio (SNDR) for the 8-bit ADC system is 55.73 dB, with the band of interest as 220 kHz and Effective number of bits(ENOB) of more than 9 bits.
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