We succeeded the true 1G1D 75" 8K4k LCD with Oxide thinfilm transistor (TFT) for the first time. The initial prototype TFT process was in Gen.6 FAB, but now, we have been developed mass producible back channel etching (BCE)-type oxide TFT process in Gen.7 FAB. As its first application, 1.7μsec pixel chargeable 1G1D 120Hz 8-domain LCD without any additional compensation part for image quality deterioration such as transmittance loss and color washout is introduced. In practical point of view, this technology can render about 20% reduction of total production material cost compare to a-Si technology.Moreover, simplified 1G1D metal line structure can contribute to production yield improvement. In this report, we present the latest AUOs Oxide TFT backplane development.

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We demonstrate high resolution the IGZO‐TFT of 4k/2k 65‐inch panel in G6 glass. Two kinds of etch‐stopper (ES) treatment power were used IGZO‐TFT, i.e., low and high power treatment (LPT and HPT), respectively. We studied the electrical characteristics of IGZO‐devices with LPT and HPT, including subthreshold slope (SS), threshold voltage (Vth), mobility, hysteresis, and Vt shift under positive and negative gate‐bias temperature stress (PBTS and NBTS) with and without light illumination, respectively. The IGZO‐TFT with HPT can be attributed to the dominant charge trapping located at GI/IGZO, IGZO/ES interface and in the IGZO film, whereas those with LPT are mainly due to charge trapping located at the GI/IGZO interface. Finally, the IGZO‐devices with LPT can simultaneously achieve low SS, Vt, and little hysteresis, and high mobility, as compared with those with HPT, moreover, those with LPT under PBTS with and without light illumination exhibited lower Vt change than those with HPT.

This paper investigates the reliability behavior of IGZO TFT with different widths under AC gate and drain stress. Device of larger width suffers from worse current degradation. By comparing the contact resistance after stress such behavior can be attributed to the damaged contact region by large current during stress. Author KeywordsReliability, voltage stress, oxide TFTs I. Objective and BackgroundRecently, amorphous indium gallium zinc oxide thin film transistors (a-IGZO TFTs) have received wide attention due to its high mobility, uniformity and low process temperature. The other potential is fabricating gate driver on array (GOA) of TFT-LCD panel. Doing so not only reduces the difficulty and cost of bonding but also facilitates the integration of process. For this application, large size a-IGZO TFT with good stability is demanded. Semiconductor energy laboratory had reported the driver-integrated panel using a-IGZO TFT [1]. In GOA operation, the TFTs are applied with pulse gate (V G ) and drain (V D ) signals, which could cause serious degradation. Therefore, for driver-integrated TFT-LCD applications, the reliability behavior of a-IGZO TFT under AC V G and V D stress should be studied carefully. In this paper, the reliability behavior of a-IGZO under pulse V G and V D signal is investigated. The device width effect of a-IGZO TFT under such stress condition is also studied. At the end the comparison and discussion of the contact resistance before and after stress is provided.

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