Integration of Back End Of Line (BEOL) CMOS technologies with Wafer Level Packaging (WLP) is challenging, as mismatch of Coefficient of Thermal Expansion (CTE) between materials can result in thermo-mechanical induced cracking. This is especially true during reflow cooling of wafers after the solder ball attach process. Factors that contribute towards cracking can be from both the BEOL as well the WLP process steps. Finite Element Analysis (FEA) of such designs can help identify possible root causes early in the design process and i.e. before actual fabrication. This would help save valuable prototyping & testing costs. In Part III of this series of FEA studies, two factors i.e. silicon nitride thickness (from the BEOL process), and the Under Bump Metalization (UBM) thickness (from the WLP process) were identified as significant factors in changing the maximum first principal stress levels in the passivation layer.
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