No abstract

power dissipation. In addition, a closed-form analytical exAn automated o&mization-based design stmtegy for 2-level pression for the noise margin of a 2-level MCML circuit is de-MOS Cuwent Mode Logic (MCML) circuits is pmposed to rived. In order to =hieve both the accuracy and S P~ goals, overcome the comolezities of the desion ~rocess. The method-the model is used to represent the design param-" 1 ology minimizes the power dissipation while satisfying the performance criteria . Moreouer, environmental and pmcess variations modeling are included in the design strategy. The impact of these variations on MCML performance as technology scales is also presented. In addition, design tips based on analytic formulation are presented for MCML designers, The proposed methodology is tested on several benchmarks belonging to optical communication and high-speed microprocessor applications built in a CMOS O.18pm process, at which the auemge ermr is within 7% between our formulation and HSPICE. 1. I n t r o d u c t i o n A logic style that is widely used in high-speed circuits; optical communication systems and high-performance micrprocessors, is MOS Current Mode Logic (MCML) [Ij. The MCML latch shown in Figure l(a) is an example of a,Z-level MCML circuit. M. generates a constant current I that is steered by the inputs to the ON branch, thus resulting in a reduced voltage swing of AV, where AV is the voltage drop across the load R (AV = I x R).etersfvariables. Moreover, a worst case variation modeling is incorporated in the design methodology and is extended to some predictive CMOS technologies. The design methodology is tested on several benchmarks designed in a CMOS 0.18pm process. For the authors' best knowledge, this is the first work to report a design strategy for 2-level MCML circuits for variabilities based on accurate device modeling while providing analysis and design guidelines for MCML designers. MCML DesignParameters The MCML performance criteria are; the voltage gain A,, noise margin N M , voltage swing ratio VSR, power dissipation Pd, and delay t,. The design variables for a 2-level MCML circuit include; the total current I , voltage swing AV, differential pairs dimensions WI, LI, W2, Lzr W3, Lal current source dimensions W., La, and the current source reference voltage V, (Figure l(a)). Expressions for the design parame ters/variahles are evaluated using the BSIM3v3 model 151. Voltage Gain (A,)A, is the mid-swing voltage gain and is given hy [SI where gm and CO, are the MOS transistor transconductance R 6 .A . . . . . . . . I : . . . . . 0 and oxide capacitance, respectively and p,, is the electrons mobility. By industrial standards, a 40% margin above unity gain is sufficient for regeneration and stabilitv in the cascaded c u m -souro, (a) 2-level MCML l . +h (b).sma!l-signal half-circuit of the 2-level MCML latch Figure I. Two-level MCML larch schematic and small-signd model. MCML circuits are characterized by their high switching speeds, constant power dissipation, and high noise immunity because of the dif...

No abstract

In this paper, we introduce a differential sensing technique for CMOS capacitive fingerprint detection. It employs a new capacitive-sensing cell structure with charge sharing detection and readout circuit. The proposed technique also can eliminate the effect of parasitic capacitances by employing parasitic insensitive switched-capacitor structure and so increases the sensitivity even under severe noisy conditions. It can also overcome the performance degradation caused by various conditions of finger surface by using a differential integrator and adjusting its number of integrations. In addition, the proposed architecture allows parallel detection of all sensing channels. It can, therefore, substantially speed up the detection process compared with conventional architectures. We implemented a prototype fingerprint sensor chip with an array of 20 × 16 sensor cells using a 130 nm CMOS process. Simulation experiments demonstrated that the proposed architecture provided an SNR gain of 54 dB, whereas a conventional single line sensing gives an SNR gain of only 13 dB.

Inspired by the huge improvement in the RF properties of CMOS, R F designers are invading the wireless market with all-CMOS R F transceivers and system-on-chip implementations. In this work, the impact of technology sealing on the RF properties of the CMOS; frequency properties, noise performance, linearity, stability, and non-quasi static egects, is investigated to plovide RF designers with an insight to the capabilities offuture CMOS technologies. Using the BSIM4 model it is found that future CMOS technologies have high prospects in the RF industry.

No abstract

No abstract

No abstract