High mobility channel materials such as Ge and III-V compound semiconductors, are explored for the sub-22nm technology node. In order to allow process integration and full scale manufacturing of these materials, they need to be introduced by epitaxial growth in narrow trenches on silicon carrier wafers. Consequently, CMP is needed to flatten the surface before constructing the gate stack. Similarly to silicon, trace contamination is expected to have a detrimental effect on the devices and therefore, an appropriate cleaning of the wafer consisting of areas with mixed substrates is an absolute requisite. This involves the removal of particulate, metallic and organic contamination while controlling surface etching of these novel materials integrated on the silicon wafer. This will be addressed in this paper and allows the development of efficient post-CMP cleaning strategies.
A novel flip-chip bonding (FCB) process was developed for improving the packaging of high frequency ICs operating at more than 10 GHz. This process, which uses multi-stacked p-Au bumps, a lower apparatus cost than that of the FCB process using PbSn bumps. Tests have confiied that the new FCB process is sufficiently reliable and that ICs made with this process has satisfactory high-frequency characteristics in IC operation of up to 15 GHz.
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